mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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b97f8ef70b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6639 3c298f89-4303-0410-b956-a3cf2f4a3e73
283 lines
7.1 KiB
C
283 lines
7.1 KiB
C
/*
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* Sonics Silicon Backplane
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* Broadcom MIPS core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
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* Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <asm/time.h>
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#include "../ssb_private.h"
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#define mips_read32(mcore, offset) ssb_read32((mcore)->dev, offset)
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#define mips_write32(mcore, offset, value) ssb_write32((mcore)->dev, offset, value)
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#define extif_read32(extif, offset) ssb_read32((extif)->dev, offset)
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#define extif_write32(extif, offset, value) ssb_write32((extif)->dev, offset, value)
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static const u32 ipsflag_irq_mask[] = {
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0,
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SSB_IPSFLAG_IRQ1,
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SSB_IPSFLAG_IRQ2,
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SSB_IPSFLAG_IRQ3,
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SSB_IPSFLAG_IRQ4,
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};
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static const u32 ipsflag_irq_shift[] = {
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0,
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SSB_IPSFLAG_IRQ1_SHIFT,
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SSB_IPSFLAG_IRQ2_SHIFT,
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SSB_IPSFLAG_IRQ3_SHIFT,
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SSB_IPSFLAG_IRQ4_SHIFT,
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};
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static inline u32 ssb_irqflag(struct ssb_device *dev)
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{
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return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
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}
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/* Get the MIPS IRQ assignment for a specified device.
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* If unassigned, 0 is returned.
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*/
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unsigned int ssb_mips_irq(struct ssb_device *dev)
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{
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struct ssb_bus *bus = dev->bus;
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u32 irqflag;
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u32 ipsflag;
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u32 tmp;
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unsigned int irq;
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irqflag = ssb_irqflag(dev);
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ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
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for (irq = 1; irq <= 4; irq++) {
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tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
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if (tmp == irqflag)
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break;
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}
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if (irq == 5)
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irq = 0;
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return irq;
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}
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static void clear_irq(struct ssb_bus *bus, unsigned int irq)
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{
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struct ssb_device *dev = bus->mipscore.dev;
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/* Clear the IRQ in the MIPScore backplane registers */
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if (irq == 0) {
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ssb_write32(dev, SSB_INTVEC, 0);
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} else {
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ssb_write32(dev, SSB_IPSFLAG,
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ssb_read32(dev, SSB_IPSFLAG) |
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ipsflag_irq_mask[irq]);
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}
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}
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static void set_irq(struct ssb_device *dev, unsigned int irq)
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{
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unsigned int oldirq = ssb_mips_irq(dev);
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struct ssb_bus *bus = dev->bus;
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struct ssb_device *mdev = bus->mipscore.dev;
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u32 irqflag = ssb_irqflag(dev);
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dev->irq = irq + 2;
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ssb_dprintk(KERN_INFO PFX
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"set_irq: core 0x%04x, irq %d => %d\n",
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dev->id.coreid, oldirq, irq);
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/* clear the old irq */
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if (oldirq == 0)
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ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
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else
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clear_irq(bus, oldirq);
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/* assign the new one */
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if (irq == 0)
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ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
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irqflag <<= ipsflag_irq_shift[irq];
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irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
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ssb_write32(mdev, SSB_IPSFLAG, irqflag);
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}
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static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
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{
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//TODO if (EXTIF available
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#if 0
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extifregs_t *eir = (extifregs_t *) regs;
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sbconfig_t *sb;
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/* Determine external UART register base */
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sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
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base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
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/* Determine IRQ */
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irq = sb_irq(sbh);
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/* Disable GPIO interrupt initially */
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W_REG(&eir->gpiointpolarity, 0);
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W_REG(&eir->gpiointmask, 0);
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/* Search for external UARTs */
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n = 2;
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for (i = 0; i < 2; i++) {
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regs = (void *) REG_MAP(base + (i * 8), 8);
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if (BCMINIT(serial_exists)(regs)) {
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/* Set GPIO 1 to be the external UART IRQ */
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W_REG(&eir->gpiointmask, 2);
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if (add)
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add(regs, irq, 13500000, 0);
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}
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}
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/* Add internal UART if enabled */
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if (R_REG(&eir->corecontrol) & CC_UE)
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if (add)
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add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
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#endif
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}
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static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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if (bus->extif.dev)
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mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
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else if (bus->chipco.dev)
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mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
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else
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mcore->nr_serial_ports = 0;
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}
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static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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mcore->flash_buswidth = 2;
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if (bus->chipco.dev) {
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mcore->flash_window = 0x1c000000;
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mcore->flash_window_size = 0x02000000;
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if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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& SSB_CHIPCO_CFG_DS16) == 0)
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mcore->flash_buswidth = 1;
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} else {
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mcore->flash_window = 0x1fc00000;
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mcore->flash_window_size = 0x00400000;
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}
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}
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static void ssb_extif_timing_init(struct ssb_extif *extif, u32 ns)
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{
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u32 tmp;
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/* Initialize extif so we can get to the LEDs and external UART */
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extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
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/* Set timing for the flash */
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tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
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tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;
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tmp |= ceildiv(120, ns);
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extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
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/* Set programmable interface timing for external uart */
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tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
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tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;
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tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT;
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tmp |= ceildiv(120, ns);
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extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
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}
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static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
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u32 *pll_type, u32 *n, u32 *m)
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{
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*pll_type = SSB_PLLTYPE_1;
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*n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
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*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
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}
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u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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if (bus->extif.dev) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (bus->chipco.dev) {
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ssb_chipco_get_clockcpu(&bus->chipco, bus->chip_id, &rate,
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&pll_type, &n, &m);
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} else
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return 0;
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if (rate == 0)
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rate = ssb_calc_clock_rate(pll_type, n, m);
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if (pll_type == SSB_PLLTYPE_6)
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rate *= 2;
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return rate;
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}
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void ssb_mipscore_init(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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struct ssb_device *dev;
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unsigned long hz, ns;
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unsigned int irq, i;
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if (!mcore->dev)
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return; /* We don't have a MIPS core */
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ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
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hz = ssb_clockspeed(bus);
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if (!hz)
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hz = 100000000;
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ns = 1000000000 / hz;
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if (bus->extif.dev)
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ssb_extif_timing_init(&bus->extif, ns);
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else if (bus->chipco.dev)
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ssb_chipco_timing_init(&bus->chipco, ns);
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/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
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for (irq = 2, i = 0; i < bus->nr_devices; i++) {
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dev = &(bus->devices[i]);
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dev->irq = ssb_mips_irq(dev) + 2;
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switch(dev->id.coreid) {
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case SSB_DEV_USB11_HOST:
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/* shouldn't need a separate irq line for non-4710, most of them have a proper
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* external usb controller on the pci */
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if ((bus->chip_id == 0x4710) && (irq <= 4)) {
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set_irq(dev, irq++);
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break;
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}
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case SSB_DEV_PCI:
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case SSB_DEV_ETHERNET:
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case SSB_DEV_80211:
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case SSB_DEV_USB20_HOST:
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/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
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if (irq <= 4) {
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set_irq(dev, irq++);
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break;
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}
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}
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}
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ssb_mips_serial_init(mcore);
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ssb_mips_flash_detect(mcore);
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}
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EXPORT_SYMBOL(ssb_mips_irq);
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