mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-05 12:30:38 +02:00
6e01c9cecf
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@786 3c298f89-4303-0410-b956-a3cf2f4a3e73
273 lines
6.9 KiB
Diff
273 lines
6.9 KiB
Diff
--- linux-2.4.30/drivers/net/b44.c 2004-08-08 01:26:05.000000000 +0200
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+++ openwrt/build_mipsel/linux-2.4.30/drivers/net/b44.c 2005-05-01 20:10:19.193354917 +0200
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@@ -1,7 +1,8 @@
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/* b44.c: Broadcom 4400 device driver.
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*
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* Copyright (C) 2002 David S. Miller (davem@redhat.com)
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- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
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+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
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+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
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*
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* Distribute under GPL.
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*/
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@@ -25,6 +26,16 @@
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#include "b44.h"
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+#include <typedefs.h>
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+#include <bcmdevs.h>
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+#include <bcmutils.h>
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+#include <osl.h>
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+#include <bcmutils.h>
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+#include <bcmnvram.h>
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+#include <sbconfig.h>
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+#include <sbchipc.h>
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+#include <sflash.h>
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+
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#define DRV_MODULE_NAME "b44"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "0.93"
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@@ -75,7 +86,7 @@
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DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
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MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
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-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
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+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
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MODULE_LICENSE("GPL");
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MODULE_PARM(b44_debug, "i");
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MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
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@@ -89,6 +100,8 @@
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
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+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ } /* terminate list with empty entry */
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};
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@@ -236,6 +249,8 @@
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udelay(1);
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}
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+static int b44_4713_instance;
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+
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static int ssb_core_unit(struct b44 *bp)
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{
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#if 0
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@@ -258,6 +273,9 @@
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break;
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};
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#endif
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+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
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+ return b44_4713_instance++;
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+ else
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return 0;
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}
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@@ -267,6 +285,28 @@
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== SBTMSLOW_CLOCK);
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}
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+static void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
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+{
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+ u32 val;
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+
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+ bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
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+ (index << CAM_CTRL_INDEX_SHIFT)));
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+
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+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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+
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+ val = br32(B44_CAM_DATA_LO);
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+
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+ data[2] = (val >> 24) & 0xFF;
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+ data[3] = (val >> 16) & 0xFF;
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+ data[4] = (val >> 8) & 0xFF;
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+ data[5] = (val >> 0) & 0xFF;
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+
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+ val = br32(B44_CAM_DATA_HI);
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+
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+ data[0] = (val >> 8) & 0xFF;
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+ data[1] = (val >> 0) & 0xFF;
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+}
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+
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static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
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{
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u32 val;
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@@ -307,6 +347,9 @@
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{
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int err;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
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bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
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(MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
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@@ -321,6 +364,9 @@
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static int b44_writephy(struct b44 *bp, int reg, u32 val)
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{
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
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bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
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(MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
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@@ -336,6 +382,9 @@
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u32 val;
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int err;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
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if (err)
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return err;
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@@ -406,6 +455,9 @@
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u32 val;
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int err;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
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goto out;
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if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
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@@ -498,6 +550,19 @@
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{
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u32 bmsr, aux;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
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+ bp->flags |= B44_FLAG_100_BASE_T;
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+ bp->flags |= B44_FLAG_FULL_DUPLEX;
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+ if (!netif_carrier_ok(bp->dev)) {
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+ u32 val = br32(B44_TX_CTRL);
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+ val |= TX_CTRL_DUPLEX;
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+ bw32(B44_TX_CTRL, val);
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+ netif_carrier_on(bp->dev);
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+ b44_link_report(bp);
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+ }
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+ return;
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+ }
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+
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if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
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!b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
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(bmsr != 0xffff)) {
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@@ -1092,6 +1157,8 @@
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/* bp->lock is held. */
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static void b44_chip_reset(struct b44 *bp)
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{
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+ unsigned int sb_clock;
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+
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if (ssb_is_core_up(bp)) {
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bw32(B44_RCV_LAZY, 0);
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bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
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@@ -1105,9 +1172,10 @@
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bw32(B44_DMARX_CTRL, 0);
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bp->rx_prod = bp->rx_cons = 0;
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} else {
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- ssb_pci_setup(bp, (bp->core_unit == 0 ?
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- SBINTVEC_ENET0 :
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- SBINTVEC_ENET1));
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+ /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/
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+ ssb_pci_setup(bp, (bp->core_unit == 0 ?
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+ SBINTVEC_ENET0 :
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+ SBINTVEC_ENET1));
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}
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ssb_core_reset(bp);
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@@ -1115,6 +1183,11 @@
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b44_clear_stats(bp);
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/* Make PHY accessible. */
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+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
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+ sb_clock = 100000000; /* 100 MHz */
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+ else
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+ sb_clock = 62500000; /* 62.5 MHz */
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+
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bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
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(0x0d & MDIO_CTRL_MAXF_MASK)));
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br32(B44_MDIO_CTRL);
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@@ -1669,20 +1742,42 @@
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{
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u8 eeprom[128];
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int err;
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+ unsigned long flags;
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- err = b44_read_eeprom(bp, &eeprom[0]);
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- if (err)
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- goto out;
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-
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- bp->dev->dev_addr[0] = eeprom[79];
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- bp->dev->dev_addr[1] = eeprom[78];
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- bp->dev->dev_addr[2] = eeprom[81];
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- bp->dev->dev_addr[3] = eeprom[80];
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- bp->dev->dev_addr[4] = eeprom[83];
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- bp->dev->dev_addr[5] = eeprom[82];
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-
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- bp->phy_addr = eeprom[90] & 0x1f;
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- bp->mdc_port = (eeprom[90] >> 14) & 0x1;
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+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
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+ /*
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+ * BCM47xx boards don't have a EEPROM. The MAC is stored in
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+ * a NVRAM area somewhere in the flash memory. As we don't
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+ * know the location and/or the format of the NVRAM area
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+ * here, we simply rely on the bootloader to write the
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+ * MAC into the CAM.
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+ */
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+ spin_lock_irqsave(&bp->lock, flags);
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+ __b44_cam_read(bp, bp->dev->dev_addr, 0);
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+ spin_unlock_irqrestore(&bp->lock, flags);
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+
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+ /*
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+ * BCM47xx boards don't have a PHY. Usually there is a switch
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+ * chip with multiple PHYs connected to the PHY port.
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+ */
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+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
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+ bp->dma_offset = 0;
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+ } else {
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+ err = b44_read_eeprom(bp, &eeprom[0]);
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+ if (err)
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+ return err;
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+
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+ bp->dev->dev_addr[0] = eeprom[79];
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+ bp->dev->dev_addr[1] = eeprom[78];
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+ bp->dev->dev_addr[2] = eeprom[81];
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+ bp->dev->dev_addr[3] = eeprom[80];
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+ bp->dev->dev_addr[4] = eeprom[83];
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+ bp->dev->dev_addr[5] = eeprom[82];
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+
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+ bp->phy_addr = eeprom[90] & 0x1f;
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+ bp->dma_offset = SB_PCI_DMA;
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+ bp->mdc_port = (eeprom[90] >> 14) & 0x1;
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+ }
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/* With this, plus the rx_header prepended to the data by the
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* hardware, we'll land the ethernet header on a 2-byte boundary.
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@@ -1692,13 +1787,12 @@
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bp->imask = IMASK_DEF;
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bp->core_unit = ssb_core_unit(bp);
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- bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
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/* XXX - really required?
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bp->flags |= B44_FLAG_BUGGY_TXPTR;
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*/
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-out:
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- return err;
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+
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+ return 0;
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}
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static int __devinit b44_init_one(struct pci_dev *pdev,
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@@ -1819,7 +1913,8 @@
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pci_save_state(bp->pdev, bp->pci_cfg_state);
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- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
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+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
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+ (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
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for (i = 0; i < 6; i++)
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printk("%2.2x%c", dev->dev_addr[i],
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i == 5 ? '\n' : ':');
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