mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 20:28:58 +02:00
2bc7082f73
iConnect board tested by: Tim Fletcher <tim@night-shade.org.uk> Wojciech Dubowik <wojciech.dubowik@neratec.com> DockStar board tested by: Martin Mueller <mm@sig21.net> RaidSonic ICY BOX NAS6210 board tested by: Luka Perkov <uboot@lukaperkov.net> SheevaPlug was not tested but support for SheevaPlug is taken from upstream uboot and it is not reported to be broken there. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32717 3c298f89-4303-0410-b956-a3cf2f4a3e73
543 lines
17 KiB
Diff
543 lines
17 KiB
Diff
http://lists.denx.de/pipermail/u-boot/2012-April/122597.html
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http://patchwork.ozlabs.org/patch/153293/
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---
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diff --git a/MAINTAINERS b/MAINTAINERS
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index 708ded7..9d2aba7 100644
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -777,6 +777,10 @@ Linus Walleij <linus.walleij@linaro.org>
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integratorap various
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integratorcp various
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+Luka Perkov <uboot@lukaperkov.net>
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+
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+ ib62x0 ARM926EJS
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+
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Dave Peverley <dpeverley@mpc-data.co.uk>
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omap730p2 ARM926EJS
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diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
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new file mode 100644
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index 0000000..d450f8d
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--- /dev/null
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+++ b/board/raidsonic/ib62x0/Makefile
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@@ -0,0 +1,43 @@
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+#
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+# (C) Copyright 2009
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+# Marvell Semiconductor <www.marvell.com>
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+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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+#
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+# See file CREDITS for list of people who contributed to this
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+# project.
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+#
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+# This program is free software; you can redistribute it and/or
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+# modify it under the terms of the GNU General Public License as
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+# published by the Free Software Foundation; either version 2 of
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+# the License, or (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+#
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+
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+include $(TOPDIR)/config.mk
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+
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+LIB = $(obj)lib$(BOARD).o
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+
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+COBJS := ib62x0.o
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+
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+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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+OBJS := $(addprefix $(obj),$(COBJS))
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+SOBJS := $(addprefix $(obj),$(SOBJS))
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+
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+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
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+
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+#########################################################################
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+
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+# defines $(obj).depend target
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+include $(SRCTREE)/rules.mk
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+
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+sinclude $(obj).depend
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+
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+#########################################################################
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diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
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new file mode 100644
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index 0000000..65f2c2e
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--- /dev/null
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+++ b/board/raidsonic/ib62x0/ib62x0.c
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@@ -0,0 +1,79 @@
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+/*
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+ * Copyright (C) 2011-2012
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+ * Gerald Kerma <dreagle@doukki.net>
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+ * Luka Perkov <uboot@lukaperkov.net>
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+ * Simon Baatz <gmbnomis@gmail.com>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <common.h>
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+#include <miiphy.h>
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/kirkwood.h>
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+#include <asm/arch/mpp.h>
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+#include "ib62x0.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int board_early_init_f(void)
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+{
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+ /*
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+ * default gpio configuration
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+ * There are maximum 64 gpios controlled through 2 sets of registers
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+ * the below configuration configures mainly initial LED status
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+ */
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+ kw_config_gpio(IB62x0_OE_VAL_LOW,
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+ IB62x0_OE_VAL_HIGH,
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+ IB62x0_OE_LOW, IB62x0_OE_HIGH);
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+
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+ /* Multi-Purpose Pins Functionality configuration */
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+ u32 kwmpp_config[] = {
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+ MPP0_NF_IO2,
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+ MPP1_NF_IO3,
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+ MPP2_NF_IO4,
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+ MPP3_NF_IO5,
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+ MPP4_NF_IO6,
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+ MPP5_NF_IO7,
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+ MPP6_SYSRST_OUTn,
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+ MPP8_TW_SDA,
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+ MPP9_TW_SCK,
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+ MPP10_UART0_TXD,
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+ MPP11_UART0_RXD,
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+ MPP18_NF_IO0,
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+ MPP19_NF_IO1,
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+ MPP20_SATA1_ACTn,
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+ MPP21_SATA0_ACTn,
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+ MPP22_GPIO, /* Power LED red */
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+ MPP24_GPIO, /* Power off device */
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+ MPP25_GPIO, /* Power LED green */
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+ MPP27_GPIO, /* USB transfer LED */
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+ MPP28_GPIO, /* Reset button */
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+ MPP29_GPIO, /* USB Copy button */
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+ 0
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+ };
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+ kirkwood_mpp_conf(kwmpp_config);
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* adress of boot parameters */
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+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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+
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+ return 0;
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+}
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diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
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new file mode 100644
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index 0000000..0c30690
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--- /dev/null
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+++ b/board/raidsonic/ib62x0/ib62x0.h
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@@ -0,0 +1,40 @@
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+/*
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+ * Copyright (C) 2011-2012
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+ * Gerald Kerma <dreagle@doukki.net>
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+ * Simon Baatz <gmbnomis@gmail.com>
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+ * Luka Perkov <uboot@lukaperkov.net>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#ifndef __IB62x0_H
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+#define __IB62x0_H
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+
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+#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
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+#define IB62x0_OE_HIGH (~(0))
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+#define IB62x0_OE_VAL_LOW 0
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+#define IB62x0_OE_VAL_HIGH 0
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+
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+/* PHY related */
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+#define MV88E1116_LED_FCTRL_REG 10
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+#define MV88E1116_CPRSP_CR3_REG 21
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+#define MV88E1116_MAC_CTRL_REG 21
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+#define MV88E1116_PGADR_REG 22
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+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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+
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+#endif /* __IB62x0_H */
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diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
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new file mode 100644
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index 0000000..bd594eb
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--- /dev/null
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+++ b/board/raidsonic/ib62x0/kwbimage.cfg
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@@ -0,0 +1,169 @@
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+#
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+# Copyright (C) 2011-2012
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+# Gerald Kerma <dreagle@doukki.net>
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+# Simon Baatz <gmbnomis@gmail.com>
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+# Luka Perkov <uboot@lukaperkov.net>
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+#
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+# See file CREDITS for list of people who contributed to this
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+# project.
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+#
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+# This program is free software; you can redistribute it and/or
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+# modify it under the terms of the GNU General Public License as
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+# published by the Free Software Foundation; either version 2 of
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+# the License, or (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+#
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+# Refer docs/README.kwimage for more details about how-to configure
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+# and create kirkwood boot image
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+#
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+
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+# Boot Media configurations
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+BOOT_FROM nand # change from nand to uart if building UART image
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+NAND_ECC_MODE default
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+NAND_PAGE_SIZE 0x0800
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+
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+# SOC registers configuration using bootrom header extension
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+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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+
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+# Configure RGMII-0 interface pad voltage to 1.8V
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+DATA 0xffd100e0 0x1b1b1b9b
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+
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+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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+DATA 0xffd01400 0x43000c30 # DDR Configuration register
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+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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+# bit23-14: 0x0,
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+# bit24: 0x1, enable exit self refresh mode on DDR access
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+# bit25: 0x1, required
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+# bit29-26: 0x0,
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+# bit31-30: 0x1,
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+
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+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
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+# bit4: 0x0, addr/cmd in smame cycle
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+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
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+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
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+# bit14: 0x0, input buffer always powered up
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+# bit18: 0x1, cpu lock transaction enabled
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+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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+# bit30-28: 0x3, required
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+# bit31: 0x0, no additional STARTBURST delay
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+
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+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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+# bit3-0: TRAS lsbs
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+# bit7-4: TRCD
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+# bit11-8: TRP
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+# bit15-12: TWR
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+# bit19-16: TWTR
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+# bit20: TRAS msb
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+# bit23-21: 0x0
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+# bit27-24: TRRD
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+# bit31-28: TRTP
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+
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+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
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+# bit6-0: TRFC
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+# bit8-7: TR2R
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+# bit10-9: TR2W
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+# bit12-11: TW2W
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+# bit31-13: 0x0, required
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+
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+DATA 0xffd01410 0x0000000c # DDR Address Control
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+# bit1-0: 00, Cs0width (x8)
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+# bit3-2: 11, Cs0size (1Gb)
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+# bit5-4: 00, Cs1width (x8)
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+# bit7-6: 11, Cs1size (1Gb)
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+# bit9-8: 00, Cs2width (nonexistent
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+# bit11-10: 00, Cs2size (nonexistent
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+# bit13-12: 00, Cs3width (nonexistent
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+# bit15-14: 00, Cs3size (nonexistent
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+# bit16: 0, Cs0AddrSel
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+# bit17: 0, Cs1AddrSel
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+# bit18: 0, Cs2AddrSel
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+# bit19: 0, Cs3AddrSel
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+# bit31-20: 0x0, required
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+
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+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
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+# bit0: 0, OpenPage enabled
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+# bit31-1: 0x0, required
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+
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+DATA 0xffd01418 0x00000000 # DDR Operation
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+# bit3-0: 0x0, DDR cmd
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+# bit31-4: 0x0, required
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+
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+DATA 0xffd0141c 0x00000c52 # DDR Mode
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+# bit2-0: 0x2, BurstLen=2 required
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+# bit3: 0x0, BurstType=0 required
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+# bit6-4: 0x4, CL=5
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+# bit7: 0x0, TestMode=0 normal
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+# bit8: 0x0, DLL reset=0 normal
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+# bit11-9: 0x6, auto-precharge write recovery ????????????
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+# bit12: 0x0, PD must be zero
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+# bit31-13: 0x0, required
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+
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+DATA 0xffd01420 0x00000040 # DDR Extended Mode
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+# bit0: 0, DDR DLL enabled
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+# bit1: 0, DDR drive strenght normal
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+# bit2: 1, DDR ODT control lsd (disabled)
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+# bit5-3: 0x0, required
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+# bit6: 0, DDR ODT control msb, (disabled)
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+# bit9-7: 0x0, required
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+# bit10: 0, differential DQS enabled
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+# bit11: 0, required
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+# bit12: 0, DDR output buffer enabled
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+# bit31-13: 0x0, required
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+
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+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
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+# bit2-0: 0x7, required
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+# bit3: 0x1, MBUS Burst Chop disabled
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+# bit6-4: 0x7, required
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+# bit7: 0x0,
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+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
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+# bit9: 0x0, no half clock cycle addition to dataout
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+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
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+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
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+# bit15-12: 0xf, required
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+# bit31-16: 0, required
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+
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+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
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+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
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+
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+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
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+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
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+# bit0: 0x1, Window enabled
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+# bit1: 0x0, Write Protect disabled
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+# bit3-2: 0x0, CS0 hit selected
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+# bit23-4: 0xfffff, required
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+# bit31-24: 0x0f, Size (i.e. 256MB)
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+
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+DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
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+DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
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+
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+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
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+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
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+
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+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
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+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
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+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
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+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
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+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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+
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+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
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+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
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+# bit3-2: 0x1, ODT1 active NEVER!
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+# bit31-4: 0x0, required
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+
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+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
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+DATA 0xffd01480 0x00000001 # DDR Initialization Control
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+# bit0: 0x1, enable DDR init upon this register write
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+
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+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
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+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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+
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+# End of Header extension
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+DATA 0x0 0x0
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diff --git a/boards.cfg b/boards.cfg
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index 3cf75c3..23f84e8 100644
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -153,6 +153,7 @@ openrd_client arm arm926ejs openrd Marvell
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openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
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rd6281a arm arm926ejs - Marvell kirkwood
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sheevaplug arm arm926ejs - Marvell kirkwood
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+ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood
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dockstar arm arm926ejs - Seagate kirkwood
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jadecpu arm arm926ejs jadecpu syteco mb86r0x
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mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
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diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
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new file mode 100644
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index 0000000..85856f2
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--- /dev/null
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+++ b/include/configs/ib62x0.h
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@@ -0,0 +1,150 @@
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+/*
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+ * Copyright (C) 2011-2012
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+ * Gerald Kerma <dreagle@doukki.net>
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+ * Luka Perkov <uboot@lukaperkov.net>
|
|
+ *
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|
+ * See file CREDITS for list of people who contributed to this
|
|
+ * project.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
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|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#ifndef _CONFIG_IB62x0_H
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+#define _CONFIG_IB62x0_H
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+
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+/*
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+ * Version number information
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+ */
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+#define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS62x0"
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+
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+/*
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+ * High level configuration options
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+ */
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+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
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+#define CONFIG_KIRKWOOD /* SOC Family Name */
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+#define CONFIG_KW88F6281 /* SOC Name */
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+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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+
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+/*
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+ * Machine type
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+ */
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+#define CONFIG_MACH_TYPE MACH_TYPE_NAS6210
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+
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+/*
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+ * Compression configuration
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+ */
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+#define CONFIG_BZIP2
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+#define CONFIG_LZMA
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+#define CONFIG_LZO
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+
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+/*
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+ * Commands configuration
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|
+ */
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+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
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+#define CONFIG_SYS_MVFS
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+#include <config_cmd_default.h>
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+#define CONFIG_CMD_ENV
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+#define CONFIG_CMD_IDE
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+#define CONFIG_CMD_MII
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+#define CONFIG_CMD_NAND
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+#define CONFIG_CMD_PING
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+#define CONFIG_CMD_USB
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+
|
|
+/*
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+ * mv-common.h should be defined after CMD configs since it used them
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|
+ * to enable certain macros
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|
+ */
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|
+#include "mv-common.h"
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+
|
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+#undef CONFIG_SYS_PROMPT
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|
+#define CONFIG_SYS_PROMPT "ib62x0 => "
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+
|
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+/*
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|
+ * Environment variables configuration
|
|
+ */
|
|
+#ifdef CONFIG_CMD_NAND
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|
+#define CONFIG_ENV_IS_IN_NAND
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|
+#define CONFIG_ENV_SECT_SIZE 0x20000
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+#else
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|
+#define CONFIG_ENV_IS_NOWHERE
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|
+#endif
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|
+#define CONFIG_ENV_SIZE 0x20000
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|
+#define CONFIG_ENV_OFFSET 0x80000
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|
+
|
|
+/*
|
|
+ * Default environment variables
|
|
+ */
|
|
+#define CONFIG_BOOTCOMMAND \
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|
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
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|
+ "ubi part rootfs; " \
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|
+ "ubifsmount rootfs; " \
|
|
+ "ubifsload 0x800000 ${kernel}; " \
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|
+ "bootm 0x800000"
|
|
+
|
|
+#define CONFIG_MTDPARTS \
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|
+ "mtdparts=orion_nand:" \
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|
+ "0x80000@0x0(uboot)," \
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|
+ "0x20000@0x80000(uboot_env)," \
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|
+ "-@0xa0000(rootfs)\0"
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|
+
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
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|
+ "console=console=ttyS0,115200\0" \
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+ "mtdids=nand0=orion_nand\0" \
|
|
+ "mtdparts="CONFIG_MTDPARTS \
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|
+ "kernel=/boot/uImage\0" \
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|
+ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
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|
+
|
|
+/*
|
|
+ * Ethernet driver configuration
|
|
+ */
|
|
+#ifdef CONFIG_CMD_NET
|
|
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
|
+#define CONFIG_PHY_BASE_ADR 0
|
|
+#undef CONFIG_RESET_PHY_R
|
|
+#endif /* CONFIG_CMD_NET */
|
|
+
|
|
+/*
|
|
+ * SATA driver configuration
|
|
+ */
|
|
+#ifdef CONFIG_CMD_IDE
|
|
+#define __io
|
|
+#define CONFIG_IDE_PREINIT
|
|
+#define CONFIG_DOS_PARTITION
|
|
+#define CONFIG_MVSATA_IDE_USE_PORT0
|
|
+#define CONFIG_MVSATA_IDE_USE_PORT1
|
|
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
|
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
|
|
+#endif /* CONFIG_CMD_IDE */
|
|
+
|
|
+/*
|
|
+ * RTC driver configuration
|
|
+ */
|
|
+#ifdef CONFIG_CMD_DATE
|
|
+#define CONFIG_RTC_MV
|
|
+#endif /* CONFIG_CMD_DATE */
|
|
+
|
|
+/*
|
|
+ * File system
|
|
+ */
|
|
+#define CONFIG_CMD_EXT2
|
|
+#define CONFIG_CMD_FAT
|
|
+#define CONFIG_CMD_JFFS2
|
|
+#define CONFIG_CMD_UBI
|
|
+#define CONFIG_CMD_UBIFS
|
|
+#define CONFIG_RBTREE
|
|
+#define CONFIG_MTD_DEVICE
|
|
+#define CONFIG_MTD_PARTITIONS
|
|
+#define CONFIG_CMD_MTDPARTS
|
|
+
|
|
+#endif /* _CONFIG_IB62x0_H */
|