mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-18 19:10:15 +03:00
f34c09e21c
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15979 3c298f89-4303-0410-b956-a3cf2f4a3e73
192 lines
6.6 KiB
Diff
192 lines
6.6 KiB
Diff
--- a/drivers/pci/Kconfig
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+++ b/drivers/pci/Kconfig
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@@ -51,6 +51,12 @@ config PCI_STUB
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When in doubt, say N.
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+config PCI_DISABLE_COMMON_QUIRKS
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+ bool "PCI disable common quirks"
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+ depends on PCI
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+ help
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+ If you don't know what to do here, say N.
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+
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config HT_IRQ
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bool "Interrupts on hypertransport devices"
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default y
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -98,6 +98,7 @@ static void __devinit quirk_resource_ali
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
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+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
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/* The Mellanox Tavor device gives false positive parity errors
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* Mark this device with a broken_parity_status, to allow
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* PCI scanning code to "skip" this now blacklisted device.
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@@ -132,11 +133,11 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_I
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/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
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but VIA don't answer queries. If you happen to have good contacts at VIA
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- ask them for me please -- Alan
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-
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- This appears to be BIOS not version dependent. So presumably there is a
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+ ask them for me please -- Alan
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+
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+ This appears to be BIOS not version dependent. So presumably there is a
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chipset level fix */
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-
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+
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static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
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{
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if (!isa_dma_bridge_buggy) {
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@@ -204,7 +205,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
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* the info on which Mr Breese based his work.
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*
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* Updated based on further information from the site and also on
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- * information provided by VIA
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+ * information provided by VIA
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*/
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static void quirk_vialatency(struct pci_dev *dev)
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{
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@@ -212,7 +213,7 @@ static void quirk_vialatency(struct pci_
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u8 busarb;
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/* Ok we have a potential problem chipset here. Now see if we have
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a buggy southbridge */
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-
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+
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p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
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if (p!=NULL) {
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/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
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@@ -227,9 +228,9 @@ static void quirk_vialatency(struct pci_
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if (p->revision < 0x10 || p->revision > 0x12)
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goto exit;
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}
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-
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+
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/*
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- * Ok we have the problem. Now set the PCI master grant to
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+ * Ok we have the problem. Now set the PCI master grant to
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* occur every master grant. The apparent bug is that under high
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* PCI load (quite common in Linux of course) you can get data
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* loss when the CPU is held off the bus for 3 bus master requests
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@@ -242,7 +243,7 @@ static void quirk_vialatency(struct pci_
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*/
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pci_read_config_byte(dev, 0x76, &busarb);
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- /* Set bit 4 and bi 5 of byte 76 to 0x01
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+ /* Set bit 4 and bi 5 of byte 76 to 0x01
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"Master priority rotation on every PCI master grant */
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busarb &= ~(1<<5);
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busarb |= (1<<4);
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@@ -285,7 +286,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VI
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* that DMA to AGP space. Latency must be set to 0xA and triton
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* workaround applied too
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* [Info kindly provided by ALi]
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- */
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+ */
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static void __init quirk_alimagik(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
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@@ -361,7 +362,7 @@ static void __devinit quirk_io_region(st
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pci_claim_resource(dev, nr);
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dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
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}
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-}
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+}
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/*
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* ATI Northbridge setups MCE the processor if you even
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@@ -418,7 +419,7 @@ static void piix4_io_quirk(struct pci_de
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/*
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* For now we only print it out. Eventually we'll want to
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* reserve it (at least if it's in the 0x1000+ range), but
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- * let's get enough confirmation reports first.
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+ * let's get enough confirmation reports first.
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*/
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base &= -size;
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dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
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@@ -443,7 +444,7 @@ static void piix4_mem_quirk(struct pci_d
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}
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/*
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* For now we only print it out. Eventually we'll want to
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- * reserve it, but let's get enough confirmation reports first.
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+ * reserve it, but let's get enough confirmation reports first.
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*/
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base &= -size;
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dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
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@@ -673,7 +674,7 @@ static void __devinit quirk_vt8235_acpi(
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
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-#ifdef CONFIG_X86_IO_APIC
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+#ifdef CONFIG_X86_IO_APIC
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#include <asm/io_apic.h>
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@@ -687,12 +688,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_V
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static void quirk_via_ioapic(struct pci_dev *dev)
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{
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u8 tmp;
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-
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+
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if (nr_ioapics < 1)
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tmp = 0; /* nothing routed to external APIC */
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else
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tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
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-
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+
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dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
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tmp == 0 ? "Disa" : "Ena");
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@@ -977,7 +978,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_C
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static void quirk_disable_pxb(struct pci_dev *pdev)
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{
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u16 config;
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-
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+
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if (pdev->revision != 0x04) /* Only C0 requires this */
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return;
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pci_read_config_word(pdev, 0x40, &config);
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@@ -1073,11 +1074,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
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* On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
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* is not activated. The myth is that Asus said that they do not want the
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* users to be irritated by just another PCI Device in the Win98 device
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- * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
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+ * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
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* package 2.7.0 for details)
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*
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- * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
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- * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
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+ * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
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+ * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
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* becomes necessary to do this tweak in two steps -- the chosen trigger
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* is either the Host bridge (preferred) or on-board VGA controller.
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*
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@@ -1229,7 +1230,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
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static void asus_hides_smbus_lpc(struct pci_dev *dev)
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{
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u16 val;
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-
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+
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if (likely(!asus_hides_smbus))
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return;
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@@ -1859,7 +1860,9 @@ static void __devinit fixup_rev1_53c810(
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
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+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
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+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
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/* Enable 1k I/O space granularity on the Intel P64H2 */
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static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
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{
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@@ -2463,6 +2466,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
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#endif /* CONFIG_PCI_IOV */
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+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
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static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
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struct pci_fixup *end)
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