mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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d0f76caa10
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19783 3c298f89-4303-0410-b956-a3cf2f4a3e73
257 lines
7.2 KiB
C
257 lines
7.2 KiB
C
/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform timer support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <asm/mach-jz4740/irq.h>
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#include <asm/mach-jz4740/jz4740.h>
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#include <asm/time.h>
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#include "clock.h"
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#define JZ_REG_TIMER_STOP 0x1C
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#define JZ_REG_TIMER_STOP_SET 0x2C
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#define JZ_REG_TIMER_STOP_CLEAR 0x3C
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#define JZ_REG_TIMER_ENABLE 0x10
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#define JZ_REG_TIMER_ENABLE_SET 0x14
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#define JZ_REG_TIMER_ENABLE_CLEAR 0x18
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#define JZ_REG_TIMER_FLAG 0x20
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#define JZ_REG_TIMER_FLAG_SET 0x24
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#define JZ_REG_TIMER_FLAG_CLEAR 0x28
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#define JZ_REG_TIMER_MASK 0x30
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#define JZ_REG_TIMER_MASK_SET 0x34
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#define JZ_REG_TIMER_MASK_CLEAR 0x38
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#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
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#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
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#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
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#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
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#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
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#define JZ_TIMER_IRQ_FULL(x) BIT(x)
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#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
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#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
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#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
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#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
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#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
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#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
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#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
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#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
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#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
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static void __iomem *jz4740_timer_base;
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static uint16_t jz4740_jiffies_per_tick;
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void jz4740_timer_enable_watchdog(void)
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{
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writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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}
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void jz4740_timer_disable_watchdog(void)
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{
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writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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}
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static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
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{
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writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
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}
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static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
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{
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writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
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}
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static void jz4740_init_timer(void)
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{
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uint16_t val = 0;
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val |= JZ_TIMER_CTRL_PRESCALE_16;
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val |= JZ_TIMER_CTRL_SRC_EXT;
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writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
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writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
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writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
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writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
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}
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static void jz4740_timer_enable(unsigned int timer)
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{
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
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}
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static void jz4740_timer_disable(unsigned int timer)
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{
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
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writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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}
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static void jz4740_timer_irq_full_enable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
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}
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static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
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{
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return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
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JZ_TIMER_IRQ_FULL(timer));
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}
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static void jz4740_timer_irq_full_disable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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}
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static void jz4740_timer_irq_half_enable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
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}
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static void jz4740_timer_irq_half_disable(unsigned int timer)
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{
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writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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}
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static cycle_t jz4740_clocksource_read(struct clocksource *cs)
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{
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uint16_t val;
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val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
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return val;
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}
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static struct clocksource jz4740_clocksource = {
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.name = "jz4740-timer",
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.rating = 200,
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.read = jz4740_clocksource_read,
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.mask = CLOCKSOURCE_MASK(16),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
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{
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struct clock_event_device *cd = devid;
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writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
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jz4740_timer_disable(0);
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cd->event_handler(cd);
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} else {
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cd->event_handler(cd);
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}
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return IRQ_HANDLED;
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}
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static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *cd)
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{
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
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writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
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case CLOCK_EVT_MODE_RESUME:
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jz4740_timer_irq_full_enable(0);
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jz4740_timer_enable(0);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_SHUTDOWN:
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jz4740_timer_disable(0);
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break;
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default:
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break;
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}
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}
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static int jz4740_clockevent_set_next(unsigned long evt, struct
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clock_event_device *cd)
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{
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writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
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writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
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jz4740_timer_enable(0);
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return 0;
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}
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static struct clock_event_device jz4740_clockevent = {
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.name = "jz4740-timer",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_next_event = jz4740_clockevent_set_next,
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.set_mode = jz4740_clockevent_set_mode,
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.rating = 200,
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.irq = JZ_IRQ_TCU0,
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};
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static struct irqaction jz_irqaction = {
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.handler = jz4740_clockevent_irq,
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.flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
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.name = "jz4740-timerirq",
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.dev_id = &jz4740_clockevent,
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};
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void __init plat_time_init(void)
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{
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int ret;
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uint32_t clk_rate;
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jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
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if (!jz4740_timer_base) {
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printk(KERN_ERR "Failed to ioremap timer registers");
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return;
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}
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clk_rate = jz4740_clock_bdata.ext_rate >> 4;
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jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
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clockevent_set_clock(&jz4740_clockevent, clk_rate);
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jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
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jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
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jz4740_clockevent.cpumask = cpumask_of(0);
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clockevents_register_device(&jz4740_clockevent);
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clocksource_set_clock(&jz4740_clocksource, clk_rate);
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ret = clocksource_register(&jz4740_clocksource);
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if (ret)
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printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
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setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
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jz4740_init_timer();
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writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
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jz4740_timer_irq_half_disable(0);
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jz4740_timer_irq_full_enable(0);
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jz4740_timer_enable(0);
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jz4740_timer_irq_half_disable(1);
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jz4740_timer_irq_full_disable(1);
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jz4740_timer_enable(1);
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}
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