mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-12 05:23:10 +02:00
d8e90848bb
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7777 3c298f89-4303-0410-b956-a3cf2f4a3e73
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
#include <linux/init.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/bootinfo.h>
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#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
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#define GPIOF 0x050000
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#define GPIOC 0x050004
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#define GPIOD 0x050008
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#define GPIO_RDY (1 << 0x08)
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#define GPIO_WPX (1 << 0x09)
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#define GPIO_ALE (1 << 0x0a)
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#define GPIO_CLE (1 << 0x0b)
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#define DEV2BASE 0x010020
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#define LO_WPX (1 << 0)
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#define LO_ALE (1 << 1)
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#define LO_CLE (1 << 2)
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#define LO_CEX (1 << 3)
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#define LO_FOFF (1 << 5)
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#define LO_SPICS (1 << 6)
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#define LO_ULED (1 << 7)
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#define MEM32(x) *((volatile unsigned *) (x))
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static void __iomem *p_nand;
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extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
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static int rb500_dev_ready(struct mtd_info *mtd)
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{
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return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
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}
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/*
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* hardware specific access to control-lines
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*
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* ctrl:
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* NAND_CLE: bit 2 -> bit 3
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* NAND_ALE: bit 3 -> bit 2
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*/
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static void rbmips_hwcontrol500(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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unsigned char orbits, nandbits;
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if (ctrl & NAND_CTRL_CHANGE) {
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orbits = (ctrl & NAND_CLE) << 1;
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orbits |= (ctrl & NAND_ALE) >> 1;
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nandbits = (~ctrl & NAND_CLE) << 1;
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nandbits |= (~ctrl & NAND_ALE) >> 1;
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changeLatchU5(orbits, nandbits);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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static struct mtd_partition partition_info[] = {
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{
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name:"RouterBoard NAND Boot",
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offset:0,
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size:4 * 1024 * 1024},
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{
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name:"RouterBoard NAND Main",
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offset:MTDPART_OFS_NXTBLK,
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size:MTDPART_SIZ_FULL}
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};
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static struct mtd_info rmtd;
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static struct nand_chip rnand;
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static unsigned init_ok = 0;
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unsigned get_rbnand_block_size(void)
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{
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if (init_ok)
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return rmtd.writesize;
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else
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return 0;
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}
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EXPORT_SYMBOL(get_rbnand_block_size);
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int __init rbmips_init(void)
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{
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int *b;
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memset(&rmtd, 0, sizeof(rmtd));
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memset(&rnand, 0, sizeof(rnand));
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printk("RB500 nand\n");
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changeLatchU5(LO_FOFF | LO_CEX,
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LO_ULED | LO_ALE | LO_CLE | LO_WPX);
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rnand.cmd_ctrl = rbmips_hwcontrol500;
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rnand.dev_ready = rb500_dev_ready;
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rnand.IO_ADDR_W = (unsigned char *)
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KSEG1ADDR(MEM32(IDT434_REG_BASE + DEV2BASE));
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rnand.IO_ADDR_R = rnand.IO_ADDR_W;
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p_nand = (void __iomem *) ioremap((void *) 0x18a20000, 0x1000);
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if (!p_nand) {
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printk("RBnand Unable ioremap buffer");
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return -ENXIO;
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}
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rnand.ecc.mode = NAND_ECC_SOFT;
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rnand.chip_delay = 25;
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rnand.options |= NAND_NO_AUTOINCR;
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rmtd.priv = &rnand;
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b = (int *) KSEG1ADDR(0x18010020);
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printk("dev2base 0x%08x mask 0x%08x c 0x%08x tc 0x%08x\n", b[0],
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b[1], b[2], b[3]);
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if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)
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&& nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
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printk("RBxxx nand device not found\n");
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iounmap((void *) p_nand);
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return -ENXIO;
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}
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add_mtd_partitions(&rmtd, partition_info, 2);
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init_ok = 1;
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return 0;
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}
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module_init(rbmips_init);
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