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411 lines
10 KiB
C
411 lines
10 KiB
C
/*
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* linux/arch/mips/jz4740/common/pm.c
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*
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* JZ4740 Power Management Routines
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/sysctl.h>
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#include <linux/suspend.h>
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#include <asm/cacheops.h>
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#include <asm/jzsoc.h>
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#undef DEBUG
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//#define DEBUG
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#ifdef DEBUG
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#define dprintk(x...) printk(x)
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#else
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#define dprintk(x...)
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#endif
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#define GPIO_WAKEUP 125 /* set SW7(GPIO 125) as WAKEUP key */
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/*
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* __gpio_as_sleep set all pins to pull-disable, and set all pins as input
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* except sdram, nand flash pins and the pins which can be used as CS1_N
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* to CS4_N for chip select.
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*/
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#define __gpio_as_sleep() \
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do { \
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REG_GPIO_PXFUNC(1) = ~0x9ff9ffff; \
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REG_GPIO_PXSELC(1) = ~0x9ff9ffff; \
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REG_GPIO_PXDIRC(1) = ~0x9ff9ffff; \
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REG_GPIO_PXPES(1) = 0xffffffff; \
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REG_GPIO_PXFUNC(2) = ~0x37000000; \
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REG_GPIO_PXSELC(2) = ~0x37000000; \
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REG_GPIO_PXDIRC(2) = ~0x37000000; \
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REG_GPIO_PXPES(2) = 0xffffffff; \
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REG_GPIO_PXFUNC(3) = 0xffffffff; \
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REG_GPIO_PXSELC(3) = 0xffffffff; \
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REG_GPIO_PXDIRC(3) = 0xffffffff; \
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REG_GPIO_PXPES(3) = 0xffffffff; \
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} while (0)
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static int jz_pm_do_hibernate(void)
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{
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/* Mask all interrupts */
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REG_INTC_IMSR = 0xffffffff;
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/*
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* RTC Wakeup or 1Hz interrupt can be enabled or disabled
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* through RTC driver's ioctl (linux/driver/char/rtc_jz.c).
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*/
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/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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REG_RTC_HWFCR = (100 << RTC_HWFCR_BIT);
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/* Set reset pin low-level assertion time after wakeup: must > 60ms */
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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REG_RTC_HRCR = (60 << RTC_HRCR_BIT); /* 60 ms */
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/* Scratch pad register to be reserved */
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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REG_RTC_HSPR = 0x12345678;
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/* clear wakeup status register */
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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REG_RTC_HWRSR = 0x0;
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/* Put CPU to power down mode */
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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REG_RTC_HCR = RTC_HCR_PD;
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while (!(REG_RTC_RCR & RTC_RCR_WRDY));
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while(1);
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/* We can't get here */
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return 0;
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}
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/* NOTES:
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* 1: Pins that are floated (NC) should be set as input and pull-enable.
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* 2: Pins that are pull-up or pull-down by outside should be set as input
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* and pull-disable.
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* 3: Pins that are connected to a chip except sdram and nand flash
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* should be set as input and pull-disable, too.
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*/
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static void jz_board_do_sleep(unsigned long *ptr)
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{
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unsigned char i;
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/* Print messages of GPIO registers for debug */
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for(i=0;i<4;i++) {
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dprintk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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/* Save GPIO registers */
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for(i = 1; i < 4; i++) {
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*ptr++ = REG_GPIO_PXFUN(i);
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*ptr++ = REG_GPIO_PXSEL(i);
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*ptr++ = REG_GPIO_PXDIR(i);
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*ptr++ = REG_GPIO_PXPE(i);
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*ptr++ = REG_GPIO_PXIM(i);
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*ptr++ = REG_GPIO_PXDAT(i);
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*ptr++ = REG_GPIO_PXTRG(i);
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}
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/*
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* Set all pins to pull-disable, and set all pins as input except
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* sdram, nand flash pins and the pins which can be used as CS1_N
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* to CS4_N for chip select.
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*/
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__gpio_as_sleep();
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/*
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* Set proper status for GPB25 to GPB28 which can be used as CS1_N to CS4_N.
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* Keep the pins' function used for chip select(CS) here according to your
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* system to avoid chip select crashing with sdram when resuming from sleep mode.
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*/
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#if defined(CONFIG_JZ4740_PAVO)
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/* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
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/* GPB26/CS2_N is connected to nand flash, needn't be changed. */
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/* GPB27/CS3_N is used as EXT_INT for CS8900 on debug board, it should be set as input.*/
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__gpio_as_input(32+27);
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/* GPB28/CS4_N is used as cs8900's chip select, shouldn't be changed. */
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#endif
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/*
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* Enable pull for NC pins here according to your system
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*/
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#if defined(CONFIG_JZ4740_PAVO)
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/* GPB30-27 <-> J1: WE_N RD_N CS4_N EXT_INT */
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for(i=27;i<31;i++) {
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__gpio_enable_pull(32+i);
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}
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/* GPC27<-> WAIT_N */
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__gpio_enable_pull(32*2+27);
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/* GPD16<->SD_WP; GPD13-10<->MSC_D0-3; GPD9<->MSC_CMD; GPD8<->MSC_CLK */
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__gpio_enable_pull(32*3+16);
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for(i=8;i<14;i++) {
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__gpio_enable_pull(32*3+i);
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}
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#endif
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/*
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* If you must set some GPIOs as output to high level or low level,
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* you can set them here, using:
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* __gpio_as_output(n);
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* __gpio_set_pin(n); or __gpio_clear_pin(n);
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*/
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#if defined(CONFIG_JZ4740_PAVO)
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/* GPD16 which is used as AMPEN_N should be set to high to disable audio amplifier */
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__gpio_set_pin(32*3+4);
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#endif
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#ifdef DEBUG
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/* Keep uart0 function for printing debug message */
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__gpio_as_uart0();
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/* Print messages of GPIO registers for debug */
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for(i=0;i<4;i++) {
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dprintk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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#endif
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}
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static void jz_board_do_resume(unsigned long *ptr)
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{
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unsigned char i;
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/* Restore GPIO registers */
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for(i = 1; i < 4; i++) {
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REG_GPIO_PXFUNS(i) = *ptr;
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REG_GPIO_PXFUNC(i) = ~(*ptr++);
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REG_GPIO_PXSELS(i) = *ptr;
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REG_GPIO_PXSELC(i) = ~(*ptr++);
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REG_GPIO_PXDIRS(i) = *ptr;
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REG_GPIO_PXDIRC(i) = ~(*ptr++);
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REG_GPIO_PXPES(i) = *ptr;
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REG_GPIO_PXPEC(i) = ~(*ptr++);
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REG_GPIO_PXIMS(i)=*ptr;
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REG_GPIO_PXIMC(i)=~(*ptr++);
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REG_GPIO_PXDATS(i)=*ptr;
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REG_GPIO_PXDATC(i)=~(*ptr++);
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REG_GPIO_PXTRGS(i)=*ptr;
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REG_GPIO_PXTRGC(i)=~(*ptr++);
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}
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/* Print messages of GPIO registers for debug */
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for(i=0;i<4;i++) {
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dprintk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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}
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static int jz_pm_do_sleep(void)
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{
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unsigned long delta;
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unsigned long nfcsr = REG_EMC_NFCSR;
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unsigned long scr = REG_CPM_SCR;
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unsigned long imr = REG_INTC_IMR;
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unsigned long sadc = REG_SADC_ENA;
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unsigned long sleep_gpio_save[7*3];
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/* Preserve current time */
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delta = xtime.tv_sec - REG_RTC_RSR;
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/* Disable nand flash */
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REG_EMC_NFCSR = ~0xff;
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/* stop sadc */
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REG_SADC_ENA &= ~0x7;
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while((REG_SADC_ENA & 0x7) != 0);
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udelay(100);
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/*stop udc and usb*/
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REG_CPM_SCR &= ~( 1<<6 | 1<<7);
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REG_CPM_SCR |= 0<<6 | 1<<7;
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/* Sleep on-board modules */
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jz_board_do_sleep(sleep_gpio_save);
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/* Mask all interrupts */
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REG_INTC_IMSR = 0xffffffff;
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/* Just allow following interrupts to wakeup the system.
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* Note: modify this according to your system.
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*/
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/* enable RTC alarm */
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__intc_unmask_irq(JZ_IRQ_RTC);
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#if 0
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/* make system wake up after n seconds by RTC alarm */
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unsigned int v, n;
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n = 10;
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while (!__rtc_write_ready());
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__rtc_enable_alarm();
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while (!__rtc_write_ready());
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__rtc_enable_alarm_irq();
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while (!__rtc_write_ready());
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v = __rtc_get_second();
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while (!__rtc_write_ready());
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__rtc_set_alarm_second(v+n);
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#endif
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/* WAKEUP key */
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__gpio_as_irq_rise_edge(GPIO_WAKEUP);
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__gpio_unmask_irq(GPIO_WAKEUP);
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__intc_unmask_irq(JZ_IRQ_GPIO3); /* IRQ_GPIOn depends on GPIO_WAKEUP */
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/* Enter SLEEP mode */
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REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
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REG_CPM_LCR |= CPM_LCR_LPM_SLEEP;
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__asm__(".set\tmips3\n\t"
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"wait\n\t"
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".set\tmips0");
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/* Restore to IDLE mode */
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REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
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REG_CPM_LCR |= CPM_LCR_LPM_IDLE;
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/* Restore nand flash control register */
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REG_EMC_NFCSR = nfcsr;
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/* Restore interrupts */
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REG_INTC_IMSR = imr;
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REG_INTC_IMCR = ~imr;
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/* Restore sadc */
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REG_SADC_ENA = sadc;
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/* Resume on-board modules */
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jz_board_do_resume(sleep_gpio_save);
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/* Restore sleep control register */
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REG_CPM_SCR = scr;
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/* Restore current time */
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xtime.tv_sec = REG_RTC_RSR + delta;
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return 0;
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}
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/* Put CPU to HIBERNATE mode */
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int jz_pm_hibernate(void)
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{
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printk("Put CPU into hibernate mode.\n");
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return jz_pm_do_hibernate();
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}
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#ifndef CONFIG_JZ_POWEROFF
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static irqreturn_t pm_irq_handler (int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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#endif
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/* Put CPU to SLEEP mode */
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int jz_pm_sleep(void)
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{
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int retval;
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#ifndef CONFIG_JZ_POWEROFF
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if ((retval = request_irq (IRQ_GPIO_0 + GPIO_WAKEUP, pm_irq_handler, IRQF_DISABLED,
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"PM", NULL))) {
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printk ("PM could not get IRQ for GPIO_WAKEUP\n");
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return retval;
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}
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#endif
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printk("Put CPU into sleep mode.\n");
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retval = jz_pm_do_sleep();
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#ifndef CONFIG_JZ_POWEROFF
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free_irq (IRQ_GPIO_0 + GPIO_WAKEUP, NULL);
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#endif
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return retval;
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}
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/*
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* valid states, only support standby(sleep) and mem(hibernate)
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*/
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static int jz_pm_valid(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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return 1;
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default:
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return 0;
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}
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}
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/*
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* Jz CPU enter save power mode
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*/
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static int jz_pm_enter(suspend_state_t state)
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{
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if (state == PM_SUSPEND_STANDBY)
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jz_pm_sleep();
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else
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jz_pm_hibernate();
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return 0;
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}
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static struct platform_suspend_ops jz_pm_ops = {
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.valid = jz_pm_valid,
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.enter = jz_pm_enter,
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};
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/*
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* Initialize power interface
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*/
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int __init jz_pm_init(void)
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{
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printk("Power Management for JZ\n");
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suspend_set_ops(&jz_pm_ops);
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return 0;
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}
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//module_init(jz_pm_init);
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