mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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08944ed54a
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21945 3c298f89-4303-0410-b956-a3cf2f4a3e73
161 lines
3.5 KiB
ArmAsm
161 lines
3.5 KiB
ArmAsm
/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */
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/* cache manipulation adapted from Broadcom code */
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/* idea taken from original bunzip2 decompressor code */
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/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */
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/* Licensed under the linux kernel's version of the GPL.*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#define KSEG0 0x80000000
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#define C0_CONFIG $16
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#define C0_TAGLO $28
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#define C0_TAGHI $29
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#define CONF1_DA_SHIFT 7 /* D$ associativity */
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#define CONF1_DA_MASK 0x00000380
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#define CONF1_DA_BASE 1
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#define CONF1_DL_SHIFT 10 /* D$ line size */
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#define CONF1_DL_MASK 0x00001c00
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#define CONF1_DL_BASE 2
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#define CONF1_DS_SHIFT 13 /* D$ sets/way */
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#define CONF1_DS_MASK 0x0000e000
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#define CONF1_DS_BASE 64
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#define CONF1_IA_SHIFT 16 /* I$ associativity */
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#define CONF1_IA_MASK 0x00070000
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#define CONF1_IA_BASE 1
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#define CONF1_IL_SHIFT 19 /* I$ line size */
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#define CONF1_IL_MASK 0x00380000
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#define CONF1_IL_BASE 2
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#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
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#define CONF1_IS_MASK 0x01c00000
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#define CONF1_IS_BASE 64
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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.text
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LEAF(startup)
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.set noreorder
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addi sp, -48
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sw a0, 16(sp)
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sw a1, 20(sp)
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sw a2, 24(sp)
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sw a3, 28(sp)
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/* Copy decompressor code to the right place */
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li t2, BZ_TEXT_START
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add a0, t2, 0
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la a1, code_start
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la a2, code_stop
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$L1:
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lw t0, 0(a1)
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sw t0, 0(a0)
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add a1, 4
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add a0, 4
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blt a1, a2, $L1
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nop
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/* At this point we need to invalidate dcache and */
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/* icache before jumping to new code */
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1: /* Get cache sizes */
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.set mips32
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mfc0 s0,C0_CONFIG,1
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.set mips0
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li s1,CONF1_DL_MASK
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and s1,s0
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beq s1,zero,nodc
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nop
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srl s1,CONF1_DL_SHIFT
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li t0,CONF1_DL_BASE
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sll s1,t0,s1 /* s1 has D$ cache line size */
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li s2,CONF1_DA_MASK
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and s2,s0
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srl s2,CONF1_DA_SHIFT
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addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */
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li t0,CONF1_DS_MASK
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and t0,s0
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srl t0,CONF1_DS_SHIFT
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li s3,CONF1_DS_BASE
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sll s3,s3,t0 /* s3 has D$ sets per way */
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multu s2,s3 /* sets/way * associativity */
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mflo t0 /* total cache lines */
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multu s1,t0 /* D$ linesize * lines */
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mflo s2 /* s2 is now D$ size in bytes */
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/* Initilize the D$: */
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mtc0 zero,C0_TAGLO
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mtc0 zero,C0_TAGHI
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li t0,KSEG0 /* Just an address for the first $ line */
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addu t1,t0,s2 /* + size of cache == end */
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.set mips3
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1: cache Index_Writeback_Inv_D,0(t0)
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.set mips0
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bne t0,t1,1b
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addu t0,s1
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nodc:
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/* Now we get to do it all again for the I$ */
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move s3,zero /* just in case there is no icache */
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move s4,zero
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li t0,CONF1_IL_MASK
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and t0,s0
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beq t0,zero,noic
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nop
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srl t0,CONF1_IL_SHIFT
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li s3,CONF1_IL_BASE
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sll s3,t0 /* s3 has I$ cache line size */
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li t0,CONF1_IA_MASK
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and t0,s0
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srl t0,CONF1_IA_SHIFT
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addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */
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li t0,CONF1_IS_MASK
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and t0,s0
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srl t0,CONF1_IS_SHIFT
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li s5,CONF1_IS_BASE
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sll s5,t0 /* s5 has I$ sets per way */
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multu s4,s5 /* sets/way * associativity */
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mflo t0 /* s4 is now total cache lines */
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multu s3,t0 /* I$ linesize * lines */
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mflo s4 /* s4 is cache size in bytes */
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/* Initilize the I$: */
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mtc0 zero,C0_TAGLO
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mtc0 zero,C0_TAGHI
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li t0,KSEG0 /* Just an address for the first $ line */
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addu t1,t0,s4 /* + size of cache == end */
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.set mips3
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1: cache Index_Invalidate_I,0(t0)
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.set mips0
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bne t0,t1,1b
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addu t0,s3
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noic:
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move a0,s3 /* icache line size */
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move a1,s4 /* icache size */
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move a2,s1 /* dcache line size */
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jal t2
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move a3,s2 /* dcache size */
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.set reorder
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END(startup)
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