mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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0dad89e259
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30527 3c298f89-4303-0410-b956-a3cf2f4a3e73
488 lines
12 KiB
C
488 lines
12 KiB
C
/*
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* Ralink RT3883 SoC PCI support
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/rt3883_regs.h>
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#define RT3883_MEMORY_BASE 0x00000000
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#define RT3883_MEMORY_SIZE 0x02000000
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#define RT3883_PCI_MEM_BASE 0x20000000
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#define RT3883_PCI_MEM_SIZE 0x10000000
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#define RT3883_PCI_IO_BASE 0x10160000
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#define RT3883_PCI_IO_SIZE 0x00010000
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#define RT3883_PCI_REG_PCICFG_ADDR 0x00
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#define RT3883_PCI_REG_PCIRAW_ADDR 0x04
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#define RT3883_PCI_REG_PCIINT_ADDR 0x08
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#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
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#define RT3833_PCI_PCIINT_PCIE BIT(20)
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#define RT3833_PCI_PCIINT_PCI1 BIT(19)
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#define RT3833_PCI_PCIINT_PCI0 BIT(18)
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#define RT3883_PCI_REG_CONFIG_ADDR 0x20
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#define RT3883_PCI_REG_CONFIG_DATA 0x24
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#define RT3883_PCI_REG_MEMBASE 0x28
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#define RT3883_PCI_REG_IOBASE 0x2c
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#define RT3883_PCI_REG_ARBCTL 0x80
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#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
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#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
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#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
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#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
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#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
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#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
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#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
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static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
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static void __iomem *rt3883_pci_base;
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static DEFINE_SPINLOCK(rt3883_pci_lock);
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static inline u32 rt3883_pci_rr(unsigned reg)
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{
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return readl(rt3883_pci_base + reg);
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}
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static inline void rt3883_pci_wr(u32 val, unsigned reg)
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{
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writel(val, rt3883_pci_base + reg);
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}
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static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
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0x80000000);
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}
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static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
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unsigned func, unsigned reg)
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{
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unsigned long flags;
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u32 address;
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u32 ret;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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spin_lock_irqsave(&rt3883_pci_lock, flags);
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rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
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ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
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spin_unlock_irqrestore(&rt3883_pci_lock, flags);
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return ret;
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}
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static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
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unsigned func, unsigned reg, u32 val)
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{
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unsigned long flags;
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u32 address;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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spin_lock_irqsave(&rt3883_pci_lock, flags);
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rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
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rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
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spin_unlock_irqrestore(&rt3883_pci_lock, flags);
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}
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static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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u32 pending;
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pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
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rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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if (pending & RT3833_PCI_PCIINT_PCI0)
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generic_handle_irq(RT3883_PCI_IRQ_PCI0);
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if (pending & RT3833_PCI_PCIINT_PCI1)
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generic_handle_irq(RT3883_PCI_IRQ_PCI1);
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if (pending & RT3833_PCI_PCIINT_PCIE)
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generic_handle_irq(RT3883_PCI_IRQ_PCIE);
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}
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static void rt3883_pci_irq_unmask(struct irq_data *d)
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{
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int irq = d->irq;
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u32 mask;
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u32 t;
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switch (irq) {
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case RT3883_PCI_IRQ_PCI0:
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mask = RT3833_PCI_PCIINT_PCI0;
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break;
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case RT3883_PCI_IRQ_PCI1:
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mask = RT3833_PCI_PCIINT_PCI1;
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break;
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case RT3883_PCI_IRQ_PCIE:
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mask = RT3833_PCI_PCIINT_PCIE;
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break;
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default:
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BUG();
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}
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t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
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rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
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/* flush write */
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rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
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}
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static void rt3883_pci_irq_mask(struct irq_data *d)
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{
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int irq = d->irq;
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u32 mask;
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u32 t;
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switch (irq) {
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case RT3883_PCI_IRQ_PCI0:
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mask = RT3833_PCI_PCIINT_PCI0;
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break;
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case RT3883_PCI_IRQ_PCI1:
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mask = RT3833_PCI_PCIINT_PCI1;
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break;
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case RT3883_PCI_IRQ_PCIE:
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mask = RT3833_PCI_PCIINT_PCIE;
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break;
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default:
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BUG();
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}
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t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
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rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
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/* flush write */
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rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
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}
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static struct irq_chip rt3883_pci_irq_chip = {
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.name = "RT3883 PCI",
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.irq_mask = rt3883_pci_irq_mask,
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.irq_unmask = rt3883_pci_irq_unmask,
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.irq_mask_ack = rt3883_pci_irq_mask,
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};
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static void __init rt3883_pci_irq_init(void)
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{
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int i;
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/* disable all interrupts */
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rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
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for (i = RT3883_PCI_IRQ_BASE;
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i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
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handle_level_irq);
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}
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irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
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}
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static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned long flags;
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u32 address;
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u32 data;
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address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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spin_lock_irqsave(&rt3883_pci_lock, flags);
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rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
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data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
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spin_unlock_irqrestore(&rt3883_pci_lock, flags);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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u32 address;
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u32 data;
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address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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spin_lock_irqsave(&rt3883_pci_lock, flags);
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rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
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data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
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switch (size) {
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case 1:
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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data = val;
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break;
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}
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rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
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spin_unlock_irqrestore(&rt3883_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops rt3883_pci_ops = {
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.read = rt3883_pci_config_read,
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.write = rt3883_pci_config_write,
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};
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static struct resource rt3883_pci_mem_resource = {
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.name = "PCI MEM space",
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.start = RT3883_PCI_MEM_BASE,
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.end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource rt3883_pci_io_resource = {
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.name = "PCI IO space",
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.start = RT3883_PCI_IO_BASE,
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.end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller rt3883_pci_controller = {
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.pci_ops = &rt3883_pci_ops,
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.mem_resource = &rt3883_pci_mem_resource,
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.io_resource = &rt3883_pci_io_resource,
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};
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static void rt3883_pci_preinit(unsigned mode)
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{
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u32 syscfg1;
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u32 rstctrl;
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u32 clkcfg1;
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if (mode & RT3883_PCI_MODE_PCIE) {
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u32 val;
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val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
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val &= ~(0x30);
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val |= (2 << 4);
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rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
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val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
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val &= ~BIT(31);
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rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
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val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
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val &= 0x80ffffff;
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rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
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val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
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val |= 0xa << 24;
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rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
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val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
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val |= BIT(31);
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rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
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msleep(50);
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}
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syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
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syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
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RT3883_SYSCFG1_PCI_HOST_MODE);
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rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
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rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
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clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
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clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
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RT3883_CLKCFG1_PCIE_CLK_EN);
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if (mode & RT3883_PCI_MODE_PCI) {
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syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
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clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
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rstctrl &= ~RT3883_RSTCTRL_PCI;
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}
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if (mode & RT3883_PCI_MODE_PCIE) {
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syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
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RT3883_SYSCFG1_PCIE_RC_MODE;
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clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
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rstctrl &= ~RT3883_RSTCTRL_PCIE;
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}
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rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
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rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
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rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
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msleep(500);
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}
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static int rt3883_pcie_ready(void)
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{
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u32 status;
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msleep(500);
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status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
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if (status & BIT(0))
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return 0;
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/* TODO: reset PCIe and turn off PCIe clock */
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return -ENODEV;
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}
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void __init rt3883_pci_init(unsigned mode)
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{
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u32 val;
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int err;
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rt3883_pci_preinit(mode);
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rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
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if (rt3883_pci_base == NULL) {
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pr_err("failed to ioremap PCI registers\n");
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return;
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}
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rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
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if (mode & RT3883_PCI_MODE_PCI)
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rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
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msleep(500);
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if (mode & RT3883_PCI_MODE_PCIE) {
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err = rt3883_pcie_ready();
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if (err)
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return;
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}
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if (mode & RT3883_PCI_MODE_PCI)
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rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
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rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
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rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
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/* PCI */
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rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
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rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
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rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
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rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
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rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
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/* PCIe */
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rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
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rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
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rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
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rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
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rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
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rt3883_pci_irq_init();
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/* PCIe */
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val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
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val |= 0x7;
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rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
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/* PCI */
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val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
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val |= 0x7;
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rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
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ioport_resource.start = rt3883_pci_io_resource.start;
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ioport_resource.end = rt3883_pci_io_resource.end;
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register_pci_controller(&rt3883_pci_controller);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = -1;
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switch (dev->bus->number) {
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case 0:
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switch (PCI_SLOT(dev->devfn)) {
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case 0x00:
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rt3883_pci_wr(0x03ff0001,
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RT3883_PCI_REG_BAR0SETUP_ADDR(0));
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rt3883_pci_wr(0x03ff0001,
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RT3883_PCI_REG_BAR0SETUP_ADDR(1));
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rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
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RT3883_MEMORY_BASE);
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rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
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irq = RT3883_CPU_IRQ_PCI;
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break;
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case 0x01:
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rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
|
|
0x00000101);
|
|
break;
|
|
case 0x11:
|
|
irq = RT3883_PCI_IRQ_PCI0;
|
|
break;
|
|
case 0x12:
|
|
irq = RT3883_PCI_IRQ_PCI1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 1:
|
|
irq = RT3883_PCI_IRQ_PCIE;
|
|
break;
|
|
|
|
default:
|
|
dev_err(&dev->dev, "no IRQ specified\n");
|
|
return irq;
|
|
}
|
|
|
|
return irq;
|
|
}
|
|
|
|
void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
|
|
{
|
|
rt3883_pci_plat_dev_init = f;
|
|
}
|
|
|
|
int pcibios_plat_dev_init(struct pci_dev *dev)
|
|
{
|
|
if (rt3883_pci_plat_dev_init)
|
|
return rt3883_pci_plat_dev_init(dev);
|
|
|
|
return 0;
|
|
}
|