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fc54b9bf15
(stable-branch of Openmoko) git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13613 3c298f89-4303-0410-b956-a3cf2f4a3e73
602 lines
18 KiB
Diff
602 lines
18 KiB
Diff
From f83b2007a1e3552a5f15faacf42f7383cd73129a Mon Sep 17 00:00:00 2001
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From: mokopatches <mokopatches@openmoko.org>
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Date: Sun, 13 Apr 2008 07:23:50 +0100
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Subject: [PATCH] introduce-fiq-basis.patch
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Adds a C-based FIQ ISR which is very convenient (and unusual --
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normally you have to do FIQ ISR in assembler only).
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Based on my article:
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http://warmcat.com/_wp/2007/09/17/at91rm9200-fiq-faq-and-simple-example-code-patch/
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Implemented as a platform device and driver.
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Suspend / resume is tested and works.
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Signed-off-by: Andy Green <andy@warmcat.com>
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---
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arch/arm/mach-s3c2440/Kconfig | 7 +
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arch/arm/mach-s3c2440/Makefile | 1 +
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arch/arm/mach-s3c2440/fiq_c_isr.c | 250 ++++++++++++++++++++++++++
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arch/arm/mach-s3c2440/fiq_c_isr.h | 64 +++++++
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arch/arm/mach-s3c2440/mach-gta02.c | 22 +++
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arch/arm/plat-s3c24xx/irq.c | 32 +++-
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include/asm-arm/arch-s3c2410/fiq_ipc_gta02.h | 28 +++
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include/asm-arm/arch-s3c2410/irqs.h | 4 +
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include/asm-arm/plat-s3c24xx/irq.h | 20 ++
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9 files changed, 426 insertions(+), 2 deletions(-)
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create mode 100644 arch/arm/mach-s3c2440/fiq_c_isr.c
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create mode 100644 arch/arm/mach-s3c2440/fiq_c_isr.h
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create mode 100644 include/asm-arm/arch-s3c2410/fiq_ipc_gta02.h
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diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
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index 1fab1c0..f7bea5d 100644
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--- a/arch/arm/mach-s3c2440/Kconfig
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+++ b/arch/arm/mach-s3c2440/Kconfig
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@@ -22,6 +22,13 @@ config S3C2440_DMA
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help
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Support for S3C2440 specific DMA code5A
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+config S3C2440_C_FIQ
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+ bool "FIQ ISR support in C"
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+ depends on ARCH_S3C2410
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+ select FIQ
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+ help
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+ Support for S3C2440 FIQ support in C -- see
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+ ./arch/arm/macs3c2440/fiq_c_isr.c
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menu "S3C2440 Machines"
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diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
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index 5305fdb..e3ca9e3 100644
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--- a/arch/arm/mach-s3c2440/Makefile
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+++ b/arch/arm/mach-s3c2440/Makefile
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@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440.o dsc.o
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obj-$(CONFIG_CPU_S3C2440) += irq.o
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obj-$(CONFIG_CPU_S3C2440) += clock.o
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obj-$(CONFIG_S3C2440_DMA) += dma.o
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+obj-$(CONFIG_S3C2440_C_FIQ) += fiq_c_isr.o
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# Machine support
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diff --git a/arch/arm/mach-s3c2440/fiq_c_isr.c b/arch/arm/mach-s3c2440/fiq_c_isr.c
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new file mode 100644
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index 0000000..12f4527
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--- /dev/null
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+++ b/arch/arm/mach-s3c2440/fiq_c_isr.c
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@@ -0,0 +1,250 @@
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+/*
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+ * Copyright 2007 Andy Green <andy@warmcat.com>
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+ * S3C modfifications
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+ * Copyright 2008 Andy Green <andy@openmoko.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <asm/hardware.h>
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+#include <asm/fiq.h>
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+#include "fiq_c_isr.h"
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+#include <linux/sysfs.h>
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+#include <linux/device.h>
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+#include <linux/platform_device.h>
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+
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+#include <asm/io.h>
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+
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+#include <asm/plat-s3c24xx/cpu.h>
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+#include <asm/plat-s3c24xx/irq.h>
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+
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+/*
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+ * Major Caveats for using FIQ
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+ * ---------------------------
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+ *
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+ * 1) it CANNOT touch any vmalloc()'d memory, only memory
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+ * that was kmalloc()'d. Static allocations in the monolithic kernel
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+ * are kmalloc()'d so they are okay. You can touch memory-mapped IO, but
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+ * the pointer for it has to have been stored in kmalloc'd memory. The
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+ * reason for this is simple: every now and then Linux turns off interrupts
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+ * and reorders the paging tables. If a FIQ happens during this time, the
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+ * virtual memory space can be partly or entirely disordered or missing.
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+ *
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+ * 2) Because vmalloc() is used when a module is inserted, THIS FIQ
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+ * ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module. But the way
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+ * it is set up, you can all to enable and disable it from your module
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+ * and intercommunicate with it through struct fiq_ipc
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+ * fiq_ipc which you can define in
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+ * asm/archfiq_ipc_type.h. The reason is the same as above, a
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+ * FIQ could happen while even the ISR is not present in virtual memory
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+ * space due to pagetables being changed at the time.
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+ *
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+ * 3) You can't call any Linux API code except simple macros
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+ * - understand that FIQ can come in at any time, no matter what
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+ * state of undress the kernel may privately be in, thinking it
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+ * locked the door by turning off interrupts... FIQ is an
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+ * unstoppable monster force (which is its value)
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+ * - they are not vmalloc()'d memory safe
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+ * - they might do crazy stuff like sleep: FIQ pisses fire and
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+ * is not interested in 'sleep' that the weak seem to need
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+ * - calling APIs from FIQ can re-enter un-renterable things
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+ * - summary: you cannot interoperate with linux APIs directly in the FIQ ISR
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+ *
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+ * If you follow these rules, it is fantastic, an extremely powerful, solid,
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+ * genuine hard realtime feature.
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+ *
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+ */
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+
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+/* more than enough to cover our jump instruction to the isr */
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+#define SIZEOF_FIQ_JUMP 8
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+/* more than enough to cover s3c2440_fiq_isr() in 4K blocks */
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+#define SIZEOF_FIQ_ISR 0x2000
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+/* increase the size of the stack that is active during FIQ as needed */
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+static u8 u8aFiqStack[4096];
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+
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+/* only one FIQ ISR possible, okay to do these here */
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+u32 _fiq_ack_mask; /* used by isr exit define */
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+unsigned long _fiq_count_fiqs; /* used by isr exit define */
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+static int _fiq_irq; /* private ; irq index we were started with, or 0 */
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+
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+/* this function must live in the monolithic kernel somewhere! A module is
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+ * NOT good enough!
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+ */
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+extern void __attribute__ ((naked)) s3c2440_fiq_isr(void);
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+
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+/* this is copied into the hard FIQ vector during init */
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+
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+static void __attribute__ ((naked)) s3c2440_FIQ_Branch(void)
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+{
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+ asm __volatile__ (
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+ "mov pc, r8 ; "
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+ );
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+}
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+
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+/* sysfs */
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+
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+static ssize_t show_count(struct device *dev, struct device_attribute *attr,
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+ char *buf)
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+{
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+ return sprintf(buf, "%ld\n", _fiq_count_fiqs);
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+}
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+
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+static DEVICE_ATTR(count, 0444, show_count, NULL);
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+
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+static struct attribute *s3c2440_fiq_sysfs_entries[] = {
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+ &dev_attr_count.attr,
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+ NULL
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+};
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+
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+static struct attribute_group s3c2440_fiq_attr_group = {
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+ .name = "fiq",
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+ .attrs = s3c2440_fiq_sysfs_entries,
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+};
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+
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+/*
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+ * call this from your kernel module to set up the FIQ ISR to service FIQs,
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+ * You need to have configured your FIQ input pin before anything will happen
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+ *
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+ * call it with, eg, IRQ_TIMER3 from asm-arm/arch-s3c2410/irqs.h
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+ *
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+ * you still need to clear the source interrupt in S3C2410_INTMSK to get
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+ * anything good happening
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+ */
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+static void fiq_init_irq_source(int irq_index_fiq)
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+{
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+ if (!irq_index_fiq) /* no interrupt */
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+ return;
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+
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+ printk(KERN_INFO"Enabling FIQ using int idx %d\n",
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+ irq_index_fiq - S3C2410_CPUIRQ_OFFSET);
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+ local_fiq_disable();
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+
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+ _fiq_irq = irq_index_fiq;
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+ _fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET);
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+
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+ /* let our selected interrupt be a magic FIQ interrupt */
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+ __raw_writel(_fiq_ack_mask, S3C2410_INTMOD);
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+
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+ /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */
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+ local_fiq_enable();
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+}
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+
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+
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+/* call this from your kernel module to disable generation of FIQ actions */
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+static void fiq_disable_irq_source(void)
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+{
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+ /* nothing makes FIQ any more */
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+ __raw_writel(0, S3C2410_INTMOD);
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+ local_fiq_disable();
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+ _fiq_irq = 0; /* no active source interrupt now either */
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+}
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+
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+/* this starts FIQ timer events... they continue until the FIQ ISR sees that
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+ * its work is done and it turns off the timer. After setting up the fiq_ipc
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+ * struct with new work, you call this to start FIQ timer actions up again.
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+ * Only the FIQ ISR decides when it is done and controls turning off the
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+ * timer events.
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+ */
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+void fiq_kick(void)
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+{
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+ unsigned long flags;
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+
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+ /* we have to take care about FIQ because this modification is
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+ * non-atomic, FIQ could come in after the read and before the
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+ * writeback and its changes to the register would be lost
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+ * (platform INTMSK mod code is taken care of already)
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+ */
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+ __raw_writel(__raw_readl(S3C2410_INTMSK) &
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+ ~(1 << (_fiq_irq - S3C2410_CPUIRQ_OFFSET)),
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+ S3C2410_INTMSK);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(fiq_kick);
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+
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+
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+
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+static int __init sc32440_fiq_probe(struct platform_device *pdev)
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+{
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+ struct resource *r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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+
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+ if (!r)
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+ return -EIO;
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+ /* configure for the interrupt we are meant to use */
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+ fiq_init_irq_source(r->start);
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+
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+ return sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
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+}
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+
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+static int sc32440_fiq_remove(struct platform_device *pdev)
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+{
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+ fiq_disable_irq_source();
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+ sysfs_remove_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
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+ return 0;
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+}
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+
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+static void fiq_set_vector_and_regs(void)
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+{
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+ struct pt_regs regs;
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+
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+ /* prep the special FIQ mode regs */
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+ memset(®s, 0, sizeof(regs));
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+ regs.ARM_r8 = (unsigned long)s3c2440_fiq_isr;
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+ regs.ARM_sp = (unsigned long)u8aFiqStack + sizeof(u8aFiqStack) - 4;
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+ /* set up the special FIQ-mode-only registers from our regs */
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+ set_fiq_regs(®s);
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+ /* copy our jump to the real ISR into the hard vector address */
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+ set_fiq_handler(s3c2440_FIQ_Branch, SIZEOF_FIQ_JUMP);
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+}
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+
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+#ifdef CONFIG_PM
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+static int sc32440_fiq_suspend(struct platform_device *pdev, pm_message_t state)
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+{
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+ /* nothing makes FIQ any more */
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+ __raw_writel(0, S3C2410_INTMOD);
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+ local_fiq_disable();
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+
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+ return 0;
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+}
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+
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+static int sc32440_fiq_resume(struct platform_device *pdev)
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+{
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+ fiq_set_vector_and_regs();
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+ fiq_init_irq_source(_fiq_irq);
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+ return 0;
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+}
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+#else
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+#define sc32440_fiq_suspend NULL
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+#define sc32440_fiq_resume NULL
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+#endif
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+
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+static struct platform_driver sc32440_fiq_driver = {
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+ .driver = {
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+ .name = "sc32440_fiq",
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+ .owner = THIS_MODULE,
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+ },
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+
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+ .probe = sc32440_fiq_probe,
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+ .remove = __devexit_p(sc32440_fiq_remove),
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+ .suspend = sc32440_fiq_suspend,
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+ .resume = sc32440_fiq_resume,
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+};
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+
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+static int __init sc32440_fiq_init(void)
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+{
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+ fiq_set_vector_and_regs();
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+
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+ return platform_driver_register(&sc32440_fiq_driver);
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+}
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+
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+static void __exit sc32440_fiq_exit(void)
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+{
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+ fiq_disable_irq_source();
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+}
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+
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+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
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+MODULE_LICENSE("GPL");
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+
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+module_init(sc32440_fiq_init);
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+module_exit(sc32440_fiq_exit);
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diff --git a/arch/arm/mach-s3c2440/fiq_c_isr.h b/arch/arm/mach-s3c2440/fiq_c_isr.h
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new file mode 100644
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index 0000000..f08740e
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--- /dev/null
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+++ b/arch/arm/mach-s3c2440/fiq_c_isr.h
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@@ -0,0 +1,64 @@
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+#ifndef _LINUX_FIQ_C_ISR_H
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+#define _LINUX_FIQ_C_ISR_H
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+
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+#include <asm/arch-s3c2410/regs-irq.h>
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+
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+extern unsigned long _fiq_count_fiqs;
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+extern u32 _fiq_ack_mask;
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+
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+/* This CANNOT be implemented in a module -- it has to be used in code
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+ * included in the monolithic kernel
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+ */
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+
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+#define FIQ_HANDLER_START() \
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+void __attribute__ ((naked)) s3c2440_fiq_isr(void) \
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+{\
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+ /*\
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+ * you can declare local vars here, take care to set the frame size\
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+ * below accordingly if there are more than a few dozen bytes of them\
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+ */\
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+
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+/* stick your locals here :-)
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+ * Do NOT initialize them here! define them and initialize them after
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+ * FIQ_HANDLER_ENTRY() is done.
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+ */
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+
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+#define FIQ_HANDLER_ENTRY(LOCALS, FRAME) \
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+ const int _FIQ_FRAME_SIZE = FRAME; \
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+ /* entry takes care to store registers we will be treading on here */\
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+ asm __volatile__ (\
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+ "mov ip, sp ;"\
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+ /* stash FIQ and r0-r8 normal regs */\
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+ "stmdb sp!, {r0-r12, lr};"\
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+ /* allow SP to get some space */\
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+ "sub sp, sp, %1 ;"\
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+ /* !! THIS SETS THE FRAME, adjust to > sizeof locals */\
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+ "sub fp, sp, %0 ;"\
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+ :\
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+ : "rI" (LOCALS), "rI" (FRAME)\
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+ :"r9"\
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+ );
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+
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+/* stick your ISR code here and then end with... */
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+
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+#define FIQ_HANDLER_END() \
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+ _fiq_count_fiqs++;\
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+ __raw_writel(_fiq_ack_mask, S3C2410_SRCPND);\
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+\
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+ /* exit back to normal mode restoring everything */\
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+ asm __volatile__ (\
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+ /* pop our allocation */\
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+ "add sp, sp, %0 ;"\
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+ /* return FIQ regs back to pristine state\
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+ * and get normal regs back\
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+ */\
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+ "ldmia sp!, {r0-r12, lr};"\
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+\
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+ /* return */\
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+ "subs pc, lr, #4;"\
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+ : \
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+ : "rI" (_FIQ_FRAME_SIZE) \
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+ );\
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+}
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+
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+#endif /* _LINUX_FIQ_C_ISR_H */
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diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
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index 46acede..0bdd0e0 100644
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--- a/arch/arm/mach-s3c2440/mach-gta02.c
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+++ b/arch/arm/mach-s3c2440/mach-gta02.c
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@@ -78,9 +78,31 @@
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#include <linux/glamofb.h>
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+#include <asm/arch/fiq_ipc_gta02.h>
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+#include "fiq_c_isr.h"
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+
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/* arbitrates which sensor IRQ owns the shared SPI bus */
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static spinlock_t motion_irq_lock;
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|
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+/* define FIQ IPC struct */
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+/*
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+ * contains stuff FIQ ISR modifies and normal kernel code can see and use
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+ * this is defined in <asm/arch/fiq_ipc_gta02.h>, you should customize
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+ * the definition in there and include the same definition in your kernel
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+ * module that wants to interoperate with your FIQ code.
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+ */
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+struct fiq_ipc fiq_ipc;
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+EXPORT_SYMBOL(fiq_ipc);
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+
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+/* define FIQ ISR */
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+
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+FIQ_HANDLER_START()
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+/* define your locals here -- no initializers though */
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+FIQ_HANDLER_ENTRY(256, 512)
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+/* Your ISR here :-) */
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+FIQ_HANDLER_END()
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+
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+
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static struct map_desc gta02_iodesc[] __initdata = {
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{
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.virtual = 0xe0000000,
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diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
|
|
index 8fbc884..82f0b04 100644
|
|
--- a/arch/arm/plat-s3c24xx/irq.c
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+++ b/arch/arm/plat-s3c24xx/irq.c
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|
@@ -133,12 +133,20 @@ static void
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s3c_irq_mask(unsigned int irqno)
|
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{
|
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unsigned long mask;
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|
-
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+#ifdef CONFIG_S3C2440_C_FIQ
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|
+ unsigned long flags;
|
|
+#endif
|
|
irqno -= IRQ_EINT0;
|
|
-
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|
+#ifdef CONFIG_S3C2440_C_FIQ
|
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+ local_save_flags(flags);
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|
+ local_fiq_disable();
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|
+#endif
|
|
mask = __raw_readl(S3C2410_INTMSK);
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|
mask |= 1UL << irqno;
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__raw_writel(mask, S3C2410_INTMSK);
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|
+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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|
+#endif
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|
}
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|
|
|
static inline void
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|
@@ -155,9 +163,19 @@ s3c_irq_maskack(unsigned int irqno)
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{
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|
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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|
unsigned long mask;
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
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|
+ unsigned long flags;
|
|
+#endif
|
|
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
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|
+ local_save_flags(flags);
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|
+ local_fiq_disable();
|
|
+#endif
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mask = __raw_readl(S3C2410_INTMSK);
|
|
__raw_writel(mask|bitval, S3C2410_INTMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_irq_restore(flags);
|
|
+#endif
|
|
|
|
__raw_writel(bitval, S3C2410_SRCPND);
|
|
__raw_writel(bitval, S3C2410_INTPND);
|
|
@@ -168,15 +186,25 @@ static void
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|
s3c_irq_unmask(unsigned int irqno)
|
|
{
|
|
unsigned long mask;
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ unsigned long flags;
|
|
+#endif
|
|
|
|
if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
|
|
irqdbf2("s3c_irq_unmask %d\n", irqno);
|
|
|
|
irqno -= IRQ_EINT0;
|
|
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_save_flags(flags);
|
|
+ local_fiq_disable();
|
|
+#endif
|
|
mask = __raw_readl(S3C2410_INTMSK);
|
|
mask &= ~(1UL << irqno);
|
|
__raw_writel(mask, S3C2410_INTMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_irq_restore(flags);
|
|
+#endif
|
|
}
|
|
|
|
struct irq_chip s3c_irq_level_chip = {
|
|
diff --git a/include/asm-arm/arch-s3c2410/fiq_ipc_gta02.h b/include/asm-arm/arch-s3c2410/fiq_ipc_gta02.h
|
|
new file mode 100644
|
|
index 0000000..341f2bb
|
|
--- /dev/null
|
|
+++ b/include/asm-arm/arch-s3c2410/fiq_ipc_gta02.h
|
|
@@ -0,0 +1,28 @@
|
|
+#ifndef _LINUX_FIQ_IPC_H
|
|
+#define _LINUX_FIQ_IPC_H
|
|
+
|
|
+/*
|
|
+ * this defines the struct which is used to communicate between the FIQ
|
|
+ * world and the normal linux kernel world. One of these structs is
|
|
+ * statically defined for you in the monolithic kernel so the FIQ ISR code
|
|
+ * can safely touch it any any time.
|
|
+ *
|
|
+ * You also want to include this file in your kernel module that wants to
|
|
+ * communicate with your FIQ code. Add any kinds of vars that are used by
|
|
+ * the FIQ ISR and the module in here.
|
|
+ *
|
|
+ * To get you started there is just an int that is incremented every FIQ
|
|
+ * you can remove this when you are ready to customize, but it is useful
|
|
+ * for testing
|
|
+ */
|
|
+
|
|
+struct fiq_ipc {
|
|
+ u8 u8a[0]; /* placeholder */
|
|
+};
|
|
+
|
|
+/* actual definition lives in arch/arm/mach-s3c2440/fiq_c_isr.c */
|
|
+extern struct fiq_ipc fiq_ipc;
|
|
+
|
|
+extern void fiq_kick(void); /* provoke a FIQ "immediately" */
|
|
+
|
|
+#endif /* _LINUX_FIQ_IPC_H */
|
|
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
|
|
index 9522cd1..ab50ffb 100644
|
|
--- a/include/asm-arm/arch-s3c2410/irqs.h
|
|
+++ b/include/asm-arm/arch-s3c2410/irqs.h
|
|
@@ -188,4 +188,8 @@
|
|
#define IRQ_GLAMO_MMC IRQ_GLAMO(7)
|
|
#define IRQ_GLAMO_RISC IRQ_GLAMO(8)
|
|
|
|
+/* offset for FIQ IRQ numbers - used by arm fiq.c */
|
|
+
|
|
+#define FIQ_START 0
|
|
+
|
|
#endif /* __ASM_ARCH_IRQ_H */
|
|
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
|
|
index 8af6d95..f70b1fc 100644
|
|
--- a/include/asm-arm/plat-s3c24xx/irq.h
|
|
+++ b/include/asm-arm/plat-s3c24xx/irq.h
|
|
@@ -23,8 +23,15 @@ s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
|
|
{
|
|
unsigned long mask;
|
|
unsigned long submask;
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ unsigned long flags;
|
|
+#endif
|
|
|
|
submask = __raw_readl(S3C2410_INTSUBMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_save_flags(flags);
|
|
+ local_fiq_disable();
|
|
+#endif
|
|
mask = __raw_readl(S3C2410_INTMSK);
|
|
|
|
submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
|
|
@@ -37,6 +44,9 @@ s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
|
|
|
|
/* write back masks */
|
|
__raw_writel(submask, S3C2410_INTSUBMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_irq_restore(flags);
|
|
+#endif
|
|
|
|
}
|
|
|
|
@@ -45,8 +55,15 @@ s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
|
|
{
|
|
unsigned long mask;
|
|
unsigned long submask;
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ unsigned long flags;
|
|
+#endif
|
|
|
|
submask = __raw_readl(S3C2410_INTSUBMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_save_flags(flags);
|
|
+ local_fiq_disable();
|
|
+#endif
|
|
mask = __raw_readl(S3C2410_INTMSK);
|
|
|
|
submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
|
|
@@ -55,6 +72,9 @@ s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
|
|
/* write back masks */
|
|
__raw_writel(submask, S3C2410_INTSUBMSK);
|
|
__raw_writel(mask, S3C2410_INTMSK);
|
|
+#ifdef CONFIG_S3C2440_C_FIQ
|
|
+ local_irq_restore(flags);
|
|
+#endif
|
|
}
|
|
|
|
|
|
--
|
|
1.5.6.5
|
|
|