mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 10:28:26 +02:00
dc3d3f1c49
it's basically also provided by ingenic and nativly based on 2.6.27, adjusted to fit into the OpenWrt-environment
302 lines
7.9 KiB
C
Executable File
302 lines
7.9 KiB
C
Executable File
/*
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* linux/arch/mips/jz4750d/board-cetus.c
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*
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* JZ4750D CETUS board setup routines.
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*
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* Copyright (c) 2006-2008 Ingenic Semiconductor Inc.
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/mm.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/reboot.h>
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#include <asm/jzsoc.h>
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/*********************************************************************************
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* Power management routines
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********************************************************************************/
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/*
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* __gpio_as_sleep set all pins to pull-disable, and set all pins as input
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* except sdram and the pins which can be used as CS1_N to CS4_N for chip select.
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*/
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#define __gpio_as_sleep() \
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do { \
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REG_GPIO_PXFUNC(1) = ~0x03ff7fff; \
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REG_GPIO_PXSELC(1) = ~0x03ff7fff; \
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REG_GPIO_PXDIRC(1) = ~0x03ff7fff; \
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REG_GPIO_PXPES(1) = ~0x03ff7fff; \
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REG_GPIO_PXFUNC(2) = ~0x01e00000; \
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REG_GPIO_PXSELC(2) = ~0x01e00000; \
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REG_GPIO_PXDIRC(2) = ~0x01e00000; \
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REG_GPIO_PXPES(2) = ~0x01e00000; \
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REG_GPIO_PXFUNC(3) = 0xffffffff; \
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REG_GPIO_PXSELC(3) = 0xffffffff; \
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REG_GPIO_PXDIRC(3) = 0xffffffff; \
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REG_GPIO_PXPES(3) = 0xffffffff; \
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REG_GPIO_PXFUNC(4) = 0xffffffff; \
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REG_GPIO_PXSELC(4) = 0xffffffff; \
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REG_GPIO_PXDIRC(4) = 0xffffffff; \
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REG_GPIO_PXPES(4) = 0xffffffff; \
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REG_GPIO_PXFUNC(5) = 0xffffffff; \
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REG_GPIO_PXSELC(5) = 0xffffffff; \
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REG_GPIO_PXDIRC(5) = 0xffffffff; \
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REG_GPIO_PXPES(5) = 0xffffffff; \
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} while (0)
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extern void (*jz_timer_callback)(void);
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struct wakeup_key_s {
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int gpio; /* gpio pin number */
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int active_low; /* the key interrupt pin is low voltage
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or fall edge acitve */
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};
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/* add wakeup keys here */
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static struct wakeup_key_s wakeup_key[] = {
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{
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.gpio = GPIO_CALL,
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.active_low = ACTIVE_LOW_CALL,
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},
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{
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.gpio = GPIO_HOME,
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.active_low = ACTIVE_LOW_HOME,
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},
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{
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.gpio = GPIO_BACK,
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.active_low = ACTIVE_LOW_BACK,
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},
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{
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.gpio = GPIO_MENU,
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.active_low = ACTIVE_LOW_MENU,
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},
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{
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.gpio = GPIO_ENDCALL,
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.active_low = ACTIVE_LOW_ENDCALL,
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},
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{
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.gpio = GPIO_ADKEY_INT,
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.active_low = ACTIVE_LOW_ADKEY,
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},
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};
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static void wakeup_key_setup(void)
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{
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int i;
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int num = sizeof(wakeup_key) / sizeof(wakeup_key[0]);
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for(i = 0; i < num; i++) {
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#if 0
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if(wakeup_key[i].active_low)
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__gpio_as_irq_fall_edge(wakeup_key[i].gpio);
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else
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__gpio_as_irq_rise_edge(wakeup_key[i].gpio);
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#endif
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__gpio_ack_irq(wakeup_key[i].gpio);
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__gpio_unmask_irq(wakeup_key[i].gpio);
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__intc_unmask_irq(IRQ_GPIO0 - (wakeup_key[i].gpio/32)); /* unmask IRQ_GPIOn */
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}
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}
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/* NOTES:
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* 1: Pins that are floated (NC) should be set as input and pull-enable.
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* 2: Pins that are pull-up or pull-down by outside should be set as input
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* and pull-disable.
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* 3: Pins that are connected to a chip except sdram and nand flash
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* should be set as input and pull-disable, too.
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*/
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void jz_board_do_sleep(unsigned long *ptr)
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{
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unsigned char i;
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#ifdef DEBUG
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__intc_unmask_irq(IRQ_UART3);
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/* Print messages of GPIO registers for debug */
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for(i=0;i<GPIO_PORT_NUM;i++) {
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printk("run dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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#endif
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/* Save GPIO registers */
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for(i = 1; i < GPIO_PORT_NUM; i++) {
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*ptr++ = REG_GPIO_PXFUN(i);
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*ptr++ = REG_GPIO_PXSEL(i);
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*ptr++ = REG_GPIO_PXDIR(i);
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*ptr++ = REG_GPIO_PXPE(i);
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}
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/*
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* Mask the ethernet irq
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*/
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// __gpio_mask_irq(GPIO_NET_INT);
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/*
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* Set all pins to pull-disable, and set all pins as input except
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* sdram and the pins which can be used as CS1_N to CS4_N for chip select.
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*/
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// __gpio_as_sleep();
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/*
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* Set proper status for GPC21 to GPC24 which can be used as CS1_N to CS4_N.
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* Keep the pins' function used for chip select(CS) here according to your
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* system to avoid chip select crashing with sdram when resuming from sleep mode.
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*/
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/* GPB25/CS1_N is used as chip select for nand flash, shouldn't be change. */
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/* GPB26/CS2_N is connected to nand flash, needn't be changed. */
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/* GPB28/CS3_N is used as cs8900's chip select, shouldn't be changed. */
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/* GPB27/CS4_N is used as NOR's chip select, shouldn't be changed. */
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/*
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* Enable pull for NC pins here according to your system
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*/
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/*
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* If you must set some GPIOs as output to high level or low level,
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* you can set them here, using:
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* __gpio_as_output(n);
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* __gpio_set_pin(n); or __gpio_clear_pin(n);
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*/
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/* AMPEN_N should be set to high to disable audio amplifier */
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__gpio_as_output(GPIO_AMPEN_N);
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__gpio_set_pin(GPIO_AMPEN_N);
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#ifdef DEBUG
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/* Keep uart function for printing debug message */
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__gpio_as_uart0();
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__gpio_as_uart1();
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/* Print messages of GPIO registers for debug */
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for(i=0;i<GPIO_PORT_NUM;i++) {
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printk("sleep dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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__intc_mask_irq(IRQ_UART1);
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#endif
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/*
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* Just allow following interrupts to wakeup the system.
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*/
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#ifdef CONFIG_RTC_CLASS
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/* enable RTC alarm */
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__intc_unmask_irq(IRQ_RTC);
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#if 0
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/* make system wake up after n seconds by RTC alarm */
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unsigned int v, n;
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n = 10;
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while (!__rtc_write_ready());
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__rtc_enable_alarm();
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while (!__rtc_write_ready());
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__rtc_enable_alarm_irq();
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while (!__rtc_write_ready());
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v = __rtc_get_second();
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while (!__rtc_write_ready());
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__rtc_set_alarm_second(v+n);
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#endif
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#endif
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/* setup wakeup keys before sleeping */
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wakeup_key_setup();
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}
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void jz_board_do_resume(unsigned long *ptr)
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{
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unsigned char i;
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/* Restore GPIO registers */
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for(i = 1; i < GPIO_PORT_NUM; i++) {
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REG_GPIO_PXFUNS(i) = *ptr;
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REG_GPIO_PXFUNC(i) = ~(*ptr++);
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REG_GPIO_PXSELS(i) = *ptr;
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REG_GPIO_PXSELC(i) = ~(*ptr++);
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REG_GPIO_PXDIRS(i) = *ptr;
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REG_GPIO_PXDIRC(i) = ~(*ptr++);
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REG_GPIO_PXPES(i) = *ptr;
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REG_GPIO_PXPEC(i) = ~(*ptr++);
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}
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#ifdef DEBUG
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/* Print messages of GPIO registers for debug */
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for(i=0;i<GPIO_PORT_NUM;i++) {
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printk("resume dat:%x pin:%x fun:%x sel:%x dir:%x pull:%x msk:%x trg:%x\n", \
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REG_GPIO_PXDAT(i),REG_GPIO_PXPIN(i),REG_GPIO_PXFUN(i),REG_GPIO_PXSEL(i), \
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REG_GPIO_PXDIR(i),REG_GPIO_PXPE(i),REG_GPIO_PXIM(i),REG_GPIO_PXTRG(i));
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}
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#endif
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}
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#if 0
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static void dancing(void)
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{
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static unsigned char slash[] = "\\|/-";
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// static volatile unsigned char *p = (unsigned char *)0xb6000058;
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static volatile unsigned char *p = (unsigned char *)0xb6000016;
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static unsigned int count = 0;
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*p = slash[count++];
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count &= 3;
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}
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static void cetus_timer_callback(void)
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{
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static unsigned long count = 0;
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if ((++count) % 50 == 0) {
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dancing();
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count = 0;
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}
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}
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#endif
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static void __init board_cpm_setup(void)
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{
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/* Stop unused module clocks here.
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* We have started all module clocks at arch/mips/jz4750d/setup.c.
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*/
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}
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static void __init board_gpio_setup(void)
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{
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/*
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* Initialize SDRAM pins
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*/
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__lcd_close_backlight();
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}
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void __init jz_board_setup(void)
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{
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printk("JZ4750D CETUS board setup\n");
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board_cpm_setup();
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board_gpio_setup();
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jz_timer_callback = NULL;//cetus_timer_callback;
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}
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/**
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* Called by arch/mips/kernel/proc.c when 'cat /proc/cpuinfo'.
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* Android requires the 'Hardware:' field in cpuinfo to setup the init.%hardware%.rc.
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*/
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const char *get_board_type(void)
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{
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return "cetus";
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}
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