mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 09:33:20 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13135 3c298f89-4303-0410-b956-a3cf2f4a3e73
580 lines
14 KiB
Diff
580 lines
14 KiB
Diff
--- a/arch/arm/mach-ixp4xx/Kconfig
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+++ b/arch/arm/mach-ixp4xx/Kconfig
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@@ -25,6 +25,14 @@ config MACH_AVILA
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Avila Network Platform. For more information on this platform,
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see <file:Documentation/arm/IXP4xx>.
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+config MACH_CAMBRIA
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+ bool "Cambria"
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+ select PCI
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+ help
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+ Say 'Y' here if you want your kernel to support the Gateworks
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+ Cambria series. For more information on this platform,
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+ see <file:Documentation/arm/IXP4xx>.
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+
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config MACH_LOFT
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bool "Loft"
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depends on MACH_AVILA
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@@ -208,7 +216,7 @@ config CPU_IXP46X
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config CPU_IXP43X
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bool
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- depends on MACH_KIXRP435
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+ depends on MACH_KIXRP435 || MACH_CAMBRIA
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default y
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config MACH_GTWX5715
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--- a/arch/arm/mach-ixp4xx/Makefile
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+++ b/arch/arm/mach-ixp4xx/Makefile
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@@ -7,6 +7,7 @@ obj-pci-n :=
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obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
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obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
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+obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
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obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
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obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
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obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
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@@ -28,6 +29,7 @@ obj-y += common.o
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obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
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obj-$(CONFIG_MACH_AVILA) += avila-setup.o
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+obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
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obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
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obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
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obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
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--- /dev/null
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+++ b/arch/arm/mach-ixp4xx/cambria-pci.c
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@@ -0,0 +1,74 @@
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+/*
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+ * arch/arch/mach-ixp4xx/cambria-pci.c
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+ *
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+ * PCI setup routines for Gateworks Cambria series
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+ *
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * based on coyote-pci.c:
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+ * Copyright (C) 2002 Jungo Software Technologies.
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+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
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+ *
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+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/init.h>
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+#include <linux/irq.h>
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+
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+#include <asm/mach-types.h>
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+#include <asm/hardware.h>
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+#include <asm/irq.h>
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+
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+#include <asm/mach/pci.h>
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+
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+extern void ixp4xx_pci_preinit(void);
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+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
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+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
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+
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+void __init cambria_pci_preinit(void)
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+{
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+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
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+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
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+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
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+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
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+
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+ ixp4xx_pci_preinit();
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+}
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+
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+static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ if (slot == 1)
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+ return IRQ_IXP4XX_GPIO11;
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+ else if (slot == 2)
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+ return IRQ_IXP4XX_GPIO10;
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+ else if (slot == 3)
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+ return IRQ_IXP4XX_GPIO9;
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+ else if (slot == 4)
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+ return IRQ_IXP4XX_GPIO8;
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+ else return -1;
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+}
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+
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+struct hw_pci cambria_pci __initdata = {
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+ .nr_controllers = 1,
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+ .preinit = cambria_pci_preinit,
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+ .swizzle = pci_std_swizzle,
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+ .setup = ixp4xx_setup,
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+ .scan = ixp4xx_scan_bus,
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+ .map_irq = cambria_map_irq,
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+};
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+
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+int __init cambria_pci_init(void)
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+{
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+ if (machine_is_cambria())
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+ pci_common_init(&cambria_pci);
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+ return 0;
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+}
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+
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+subsys_initcall(cambria_pci_init);
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--- /dev/null
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+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
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@@ -0,0 +1,444 @@
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+/*
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+ * arch/arm/mach-ixp4xx/cambria-setup.c
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+ *
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+ * Board setup for the Gateworks Cambria series
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+ *
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+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
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+ *
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+ * based on coyote-setup.c:
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+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
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+ *
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+ * Author: Imre Kaloz <Kaloz@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/device.h>
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+#include <linux/if_ether.h>
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+#include <linux/socket.h>
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+#include <linux/netdevice.h>
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+#include <linux/serial.h>
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+#include <linux/tty.h>
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+#include <linux/serial_8250.h>
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+#include <linux/slab.h>
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+#ifdef CONFIG_SENSORS_EEPROM
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+# include <linux/i2c.h>
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+# include <linux/eeprom.h>
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+#endif
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+
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+#include <linux/leds.h>
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+#include <linux/i2c-gpio.h>
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+#include <asm/types.h>
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+#include <asm/setup.h>
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+#include <asm/memory.h>
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+#include <asm/hardware.h>
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+#include <asm/irq.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/flash.h>
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+
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+struct cambria_board_info {
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+ unsigned char *model;
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+ void (* setup)(void);
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+};
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+
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+static struct cambria_board_info *cambria_info __initdata;
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+
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+static struct flash_platform_data cambria_flash_data = {
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+ .map_name = "cfi_probe",
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+ .width = 2,
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+};
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+
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+static struct resource cambria_flash_resource = {
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct platform_device cambria_flash = {
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+ .name = "IXP4XX-Flash",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = &cambria_flash_data,
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+ },
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+ .num_resources = 1,
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+ .resource = &cambria_flash_resource,
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+};
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+
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+static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
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+ .sda_pin = 7,
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+ .scl_pin = 6,
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+};
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+
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+static struct platform_device cambria_i2c_gpio = {
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+ .name = "i2c-gpio",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = &cambria_i2c_gpio_data,
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+ },
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+};
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+
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+static struct resource cambria_uart_resource = {
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+ .start = IXP4XX_UART1_BASE_PHYS,
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+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct plat_serial8250_port cambria_uart_data[] = {
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+ {
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+ .mapbase = IXP4XX_UART1_BASE_PHYS,
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+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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+ .irq = IRQ_IXP4XX_UART1,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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+ .iotype = UPIO_MEM,
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+ .regshift = 2,
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+ .uartclk = IXP4XX_UART_XTAL,
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+ },
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+ { },
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+};
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+
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+static struct platform_device cambria_uart = {
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+ .name = "serial8250",
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+ .id = PLAT8250_DEV_PLATFORM,
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+ .dev = {
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+ .platform_data = cambria_uart_data,
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+ },
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+ .num_resources = 1,
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+ .resource = &cambria_uart_resource,
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+};
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+
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+static struct resource cambria_pata_resources[] = {
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+ {
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+ .flags = IORESOURCE_MEM
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+ },
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+ {
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "intrq",
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+ .start = IRQ_IXP4XX_GPIO12,
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+ .end = IRQ_IXP4XX_GPIO12,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct ixp4xx_pata_data cambria_pata_data = {
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+ .cs0_bits = 0xbfff3c03,
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+ .cs1_bits = 0xbfff3c03,
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+};
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+
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+static struct platform_device cambria_pata = {
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+ .name = "pata_ixp4xx_cf",
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+ .id = 0,
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+ .dev.platform_data = &cambria_pata_data,
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+ .num_resources = ARRAY_SIZE(cambria_pata_resources),
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+ .resource = cambria_pata_resources,
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+};
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+
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+static struct eth_plat_info cambria_npec_data = {
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+ .phy = 1,
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+ .rxq = 4,
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+ .txreadyq = 21,
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+};
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+
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+static struct eth_plat_info cambria_npea_data = {
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+ .phy = 2,
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+ .rxq = 2,
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+ .txreadyq = 19,
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+};
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+
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+static struct platform_device cambria_npec_device = {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEC,
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+ .dev.platform_data = &cambria_npec_data,
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+};
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+
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+static struct platform_device cambria_npea_device = {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEA,
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+ .dev.platform_data = &cambria_npea_data,
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+};
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+
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+static struct gpio_led cambria_gpio_leds[] = {
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+ {
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+ .name = "user", /* green led */
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+ .gpio = 5,
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+ .active_low = 1,
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+ }
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+};
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+
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+static struct gpio_led_platform_data cambria_gpio_leds_data = {
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+ .num_leds = 1,
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+ .leds = cambria_gpio_leds,
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+};
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+
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+static struct platform_device cambria_gpio_leds_device = {
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+ .name = "leds-gpio",
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+ .id = -1,
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+ .dev.platform_data = &cambria_gpio_leds_data,
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+};
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+
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+
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+static struct latch_led cambria_latch_leds[] = {
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+ {
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+ .name = "ledA", /* green led */
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+ .bit = 0,
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+ },
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+ {
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+ .name = "ledB", /* green led */
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+ .bit = 1,
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+ },
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+ {
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+ .name = "ledC", /* green led */
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+ .bit = 2,
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+ },
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+ {
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+ .name = "ledD", /* green led */
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+ .bit = 3,
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+ },
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+ {
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+ .name = "ledE", /* green led */
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+ .bit = 4,
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+ },
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+ {
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+ .name = "ledF", /* green led */
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+ .bit = 5,
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+ },
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+ {
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+ .name = "ledG", /* green led */
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+ .bit = 6,
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+ },
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+ {
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+ .name = "ledH", /* green led */
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+ .bit = 7,
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+ }
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+};
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+
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+static struct latch_led_platform_data cambria_latch_leds_data = {
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+ .num_leds = 8,
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+ .leds = cambria_latch_leds,
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+ .mem = 0x53F40000,
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+};
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+
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+static struct platform_device cambria_latch_leds_device = {
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+ .name = "leds-latch",
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+ .id = -1,
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+ .dev.platform_data = &cambria_latch_leds_data,
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+};
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+
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+static struct resource cambria_usb0_resources[] = {
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+ {
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+ .start = 0xCD000000,
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+ .end = 0xCD000300,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = 32,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct resource cambria_usb1_resources[] = {
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+ {
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+ .start = 0xCE000000,
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+ .end = 0xCE000300,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = 33,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 ehci_dma_mask = ~(u32)0;
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+
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+static struct platform_device cambria_usb0_device = {
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+ .name = "ixp4xx-ehci",
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+ .id = 0,
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+ .resource = cambria_usb0_resources,
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+ .num_resources = ARRAY_SIZE(cambria_usb0_resources),
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+ .dev = {
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+ .dma_mask = &ehci_dma_mask,
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+ .coherent_dma_mask = 0xffffffff,
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+ },
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+};
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+
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+static struct platform_device cambria_usb1_device = {
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+ .name = "ixp4xx-ehci",
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+ .id = 1,
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+ .resource = cambria_usb1_resources,
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+ .num_resources = ARRAY_SIZE(cambria_usb1_resources),
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+ .dev = {
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+ .dma_mask = &ehci_dma_mask,
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+ .coherent_dma_mask = 0xffffffff,
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+ },
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+};
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+
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+static struct platform_device *cambria_devices[] __initdata = {
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+ &cambria_i2c_gpio,
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+ &cambria_flash,
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+ &cambria_uart,
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+};
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+
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+static void __init cambria_gw23xx_setup(void)
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+{
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+ platform_device_register(&cambria_npec_device);
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+ platform_device_register(&cambria_npea_device);
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+}
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+
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+#ifdef CONFIG_SENSORS_EEPROM
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+static void __init cambria_gw2350_setup(void)
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+{
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+ platform_device_register(&cambria_npec_device);
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+ platform_device_register(&cambria_npea_device);
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+
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+ platform_device_register(&cambria_usb0_device);
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+ platform_device_register(&cambria_usb1_device);
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+
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+ platform_device_register(&cambria_gpio_leds_device);
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+}
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+
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+static void __init cambria_gw2358_setup(void)
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+{
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+ platform_device_register(&cambria_npec_device);
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+ platform_device_register(&cambria_npea_device);
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+
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+ platform_device_register(&cambria_usb0_device);
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+ platform_device_register(&cambria_usb1_device);
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+
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+ platform_device_register(&cambria_pata);
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+
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+ platform_device_register(&cambria_latch_leds_device);
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+}
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+
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+static struct cambria_board_info cambria_boards[] __initdata = {
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+ {
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+ .model = "GW2350",
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+ .setup = cambria_gw2350_setup,
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+ }, {
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+ .model = "GW2358",
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+ .setup = cambria_gw2358_setup,
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+ }
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+};
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+
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+static struct cambria_board_info * __init cambria_find_board_info(char *model)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
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+ struct cambria_board_info *info = &cambria_boards[i];
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+ if (strncmp(info->model, model, strlen(info->model)) == 0)
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+ return info;
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+ }
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+
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+ return NULL;
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+}
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+
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+struct cambria_eeprom_header {
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+ unsigned char mac0[ETH_ALEN];
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+ unsigned char mac1[ETH_ALEN];
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+ unsigned char res0[4];
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+ unsigned char magic[2];
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+ unsigned char config[14];
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+ unsigned char model[16];
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+};
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+
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+static int __init cambria_eeprom_notify(struct notifier_block *self,
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+ unsigned long event, void *t)
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+{
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+ struct eeprom_data *ee = t;
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+ struct cambria_eeprom_header hdr;
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+
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+ if (cambria_info)
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+ return NOTIFY_DONE;
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+
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+ /* The eeprom is at address 0x51 */
|
|
+ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
|
|
+ return NOTIFY_DONE;
|
|
+
|
|
+ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
|
|
+ 0, sizeof(hdr));
|
|
+
|
|
+ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
|
|
+ return NOTIFY_DONE;
|
|
+
|
|
+ memcpy(&cambria_npec_data.hwaddr, hdr.mac0, ETH_ALEN);
|
|
+ memcpy(&cambria_npea_data.hwaddr, hdr.mac1, ETH_ALEN);
|
|
+
|
|
+ cambria_info = cambria_find_board_info(hdr.model);
|
|
+
|
|
+ return NOTIFY_OK;
|
|
+}
|
|
+
|
|
+static struct notifier_block cambria_eeprom_notifier __initdata = {
|
|
+ .notifier_call = cambria_eeprom_notify
|
|
+};
|
|
+
|
|
+static void __init cambria_register_eeprom_notifier(void)
|
|
+{
|
|
+ register_eeprom_notifier(&cambria_eeprom_notifier);
|
|
+}
|
|
+
|
|
+static void __init cambria_unregister_eeprom_notifier(void)
|
|
+{
|
|
+ unregister_eeprom_notifier(&cambria_eeprom_notifier);
|
|
+}
|
|
+#else /* CONFIG_SENSORS_EEPROM */
|
|
+static inline void cambria_register_eeprom_notifier(void) {};
|
|
+static inline void cambria_unregister_eeprom_notifier(void) {};
|
|
+#endif /* CONFIG_SENSORS_EEPROM */
|
|
+
|
|
+static void __init cambria_init(void)
|
|
+{
|
|
+ ixp4xx_sys_init();
|
|
+
|
|
+ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
|
|
+ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
|
|
+
|
|
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
|
|
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
|
|
+
|
|
+ platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
|
|
+
|
|
+ cambria_pata_resources[0].start = 0x53e00000;
|
|
+ cambria_pata_resources[0].end = 0x53e3ffff;
|
|
+
|
|
+ cambria_pata_resources[1].start = 0x53e40000;
|
|
+ cambria_pata_resources[1].end = 0x53e7ffff;
|
|
+
|
|
+ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
|
|
+ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
|
|
+
|
|
+ cambria_register_eeprom_notifier();
|
|
+}
|
|
+
|
|
+static int __init cambria_model_setup(void)
|
|
+{
|
|
+ if (!machine_is_cambria())
|
|
+ return 0;
|
|
+
|
|
+ if (cambria_info) {
|
|
+ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
|
|
+ cambria_info->model);
|
|
+ cambria_info->setup();
|
|
+ } else {
|
|
+ printk(KERN_INFO "Unknown/missing Cambria model number"
|
|
+ " -- defaults will be used\n");
|
|
+ cambria_gw23xx_setup();
|
|
+ }
|
|
+
|
|
+ cambria_unregister_eeprom_notifier();
|
|
+ return 0;
|
|
+}
|
|
+late_initcall(cambria_model_setup);
|
|
+
|
|
+#ifdef CONFIG_MACH_CAMBRIA
|
|
+MACHINE_START(CAMBRIA, "Gateworks Cambria series")
|
|
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
|
|
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
|
|
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
|
|
+ .map_io = ixp4xx_map_io,
|
|
+ .init_irq = ixp4xx_init_irq,
|
|
+ .timer = &ixp4xx_timer,
|
|
+ .boot_params = 0x0100,
|
|
+ .init_machine = cambria_init,
|
|
+MACHINE_END
|
|
+#endif
|
|
--- a/include/asm-arm/arch-ixp4xx/hardware.h
|
|
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
|
|
@@ -18,7 +18,7 @@
|
|
#define __ASM_ARCH_HARDWARE_H__
|
|
|
|
#define PCIBIOS_MIN_IO 0x00001000
|
|
-#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
|
|
+#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
|
|
|
|
/*
|
|
* We override the standard dma-mask routines for bouncing.
|