mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 09:43:40 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13619 3c298f89-4303-0410-b956-a3cf2f4a3e73
432 lines
14 KiB
Diff
Executable File
432 lines
14 KiB
Diff
Executable File
From 9ada9a3247ca02a0dddeae24a07a2744690aeb51 Mon Sep 17 00:00:00 2001
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From: Andy Green <andy@openmoko.com>
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Date: Fri, 25 Jul 2008 23:06:15 +0100
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Subject: [PATCH] fix-glamo-suspend-resume-dram-and-engines.patch
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Two issues... we never took care to take down engines in suspend
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and bring them back in resume. This was part of the display
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corruption that could be seen briefly on resume. The other issue
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that made the "noise" corruption was bad ordering of resume steps.
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This patch simplifies (removing needless re-init) resume actions
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and makes explicit the suspend and resume steps. It also adds
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code to track which engines are up and push them down in suspend
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and bring them back in resume.
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The result is no more corruption of display buffer in suspend, it
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comes back completely clean.
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Signed-off-by: Andy Green <andy@openmoko.com>
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---
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drivers/mfd/glamo/glamo-core.c | 269 +++++++++++++++++++---------------------
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drivers/mfd/glamo/glamo-core.h | 2 +
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drivers/mfd/glamo/glamo-regs.h | 6 +-
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3 files changed, 137 insertions(+), 140 deletions(-)
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diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
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index d4b526d..ee33901 100644
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--- a/drivers/mfd/glamo/glamo-core.c
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+++ b/drivers/mfd/glamo/glamo-core.c
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@@ -54,6 +54,8 @@
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#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
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+#define GLAMO_MEM_REFRESH_COUNT 0x100
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+
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static struct glamo_core *glamo_handle;
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static inline void __reg_write(struct glamo_core *glamo,
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@@ -381,9 +383,8 @@ out_unlock:
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* 'engine' support
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***********************************************************************/
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-int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
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+int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
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{
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- spin_lock(&glamo->lock);
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switch (engine) {
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case GLAMO_ENGINE_LCD:
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__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
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@@ -432,27 +433,59 @@ int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
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default:
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break;
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}
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- spin_unlock(&glamo->lock);
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+
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+ glamo->engine_enabled_bitfield |= 1 << engine;
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return 0;
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}
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-EXPORT_SYMBOL_GPL(glamo_engine_enable);
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-int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
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+int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
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{
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+ int ret;
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+
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spin_lock(&glamo->lock);
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+
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+ ret = __glamo_engine_enable(glamo, engine);
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+
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+ spin_unlock(&glamo->lock);
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+
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+ return ret;
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+}
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+EXPORT_SYMBOL_GPL(glamo_engine_enable);
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+
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+int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
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+{
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switch (engine) {
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+ case GLAMO_ENGINE_LCD:
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+ /* remove pixel clock to LCM */
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+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
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+ GLAMO_CLOCK_LCD_EN_DCLK, 0);
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+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
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+ GLAMO_CLOCK_LCD_EN_DHCLK |
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+ GLAMO_CLOCK_LCD_EN_DMCLK, 0);
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+ /* kill memory clock */
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+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
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+ GLAMO_CLOCK_LCD_EN_M5CLK, 0);
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+ /* stop dividing the clocks */
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+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
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+ GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
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+ GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
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+ GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
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+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
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+ GLAMO_HOSTBUS2_MMIO_EN_LCD, 0);
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+ break;
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+
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case GLAMO_ENGINE_MMC:
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__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC, 0,
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GLAMO_CLOCK_MMC_EN_M9CLK |
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GLAMO_CLOCK_MMC_EN_TCLK |
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GLAMO_CLOCK_MMC_DG_M9CLK |
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GLAMO_CLOCK_MMC_DG_TCLK);
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- __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2), 0,
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- GLAMO_HOSTBUS2_MMIO_EN_MMC);
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/* disable the TCLK divider clk input */
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__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0,
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GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
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+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2), 0,
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+ GLAMO_HOSTBUS2_MMIO_EN_MMC);
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/* good idea to hold the thing in reset when we power it off? */
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/* writew(readw(glamo->base + GLAMO_REG_CLOCK_MMC) |
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GLAMO_CLOCK_MMC_RESET, glamo->base + GLAMO_REG_CLOCK_MMC);
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@@ -461,10 +494,23 @@ int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
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default:
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break;
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}
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- spin_unlock(&glamo->lock);
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+
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+ glamo->engine_enabled_bitfield &= ~(1 << engine);
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return 0;
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}
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+int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
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+{
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+ int ret;
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+
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+ spin_lock(&glamo->lock);
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+
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+ ret = __glamo_engine_disable(glamo, engine);
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+
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+ spin_unlock(&glamo->lock);
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+
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+ return ret;
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+}
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EXPORT_SYMBOL_GPL(glamo_engine_disable);
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struct glamo_script reset_regs[] = {
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@@ -618,7 +664,7 @@ int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
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if (may_sleep)
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msleep(line->val);
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else
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- mdelay(line->val);
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+ mdelay(line->val * 4);
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break;
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case 0xfffd:
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/* spin until PLLs lock */
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@@ -717,111 +763,17 @@ static struct glamo_script glamo_init_script[] = {
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{ GLAMO_REG_CLOCK_MEMORY, 0x000b },
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};
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-static struct glamo_script glamo_resume_script[] = {
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- { GLAMO_REG_IRQ_ENABLE, 0x01ff },
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- { GLAMO_REG_CLOCK_GEN6, 0x2000 },
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- { GLAMO_REG_CLOCK_GEN7, 0x0001 }, /* 0101 */
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- { GLAMO_REG_CLOCK_GEN8, 0x0100 },
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- { GLAMO_REG_CLOCK_HOST, 0x000d },
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- { 0x200, 0x0ef0 },
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- { 0x202, 0x07ff },
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- { 0x212, 0x0000 },
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- { 0x214, 0x4000 },
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- { 0x216, 0xf00e },
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- { GLAMO_REG_MEM_TYPE, 0x0874 }, /* 8MB, 16 word pg wr+rd */
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- { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
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-
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- { GLAMO_REG_MEM_TIMING1, 0x0108 },
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- { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
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- { GLAMO_REG_MEM_TIMING3, 0x0000 },
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- { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
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- { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
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- { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
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- { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
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- { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
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- { GLAMO_REG_MEM_TIMING9, 0x6006 },
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- { GLAMO_REG_MEM_TIMING10, 0x00ff },
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- { GLAMO_REG_MEM_TIMING11, 0x0001 },
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- { GLAMO_REG_MEM_POWER1, 0x0020 },
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- { GLAMO_REG_MEM_POWER2, 0x0000 },
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- { GLAMO_REG_MEM_DRAM1, 0x0000 },
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- { 0xfffe, 1 },
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- { GLAMO_REG_MEM_DRAM1, 0xc100 },
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- { 0xfffe, 1 },
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- { GLAMO_REG_MEM_DRAM1, 0xe100 },
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- { GLAMO_REG_MEM_DRAM2, 0x01d6 },
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- { GLAMO_REG_CLOCK_MEMORY, 0x000b },
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-};
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-
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-#if 0 /* MM370 */
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-static const struct glamo_script regs_vram_2mb = {
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- { GLAMO_REG_CLOCK_MEMORY, 0x3aaa },
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- { 0xfffe, 50 },
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- { GLAMO_REG_CLOCK_MEMORY, 0x0aaa },
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- { 0xfffe, 3 },
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- { GLAMO_REG_MEM_POWER1, 0x0020 },
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- { 0x033a, 0x0000 },
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- { 0x033c, 0x0000 },
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- { 0x033e, 0x0000 },
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- { 0x0340, 0x0000 },
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- { 0x0342, 0x0000 },
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- { 0x0344, 0x0000 },
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- { 0x0346, 0x0240 },
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- { GLAMO_REG_MEM_TIMING8, 0x1016 },
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- { GLAMO_REG_MEM_TIMING9, 0x6067 },
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- { GLAMO_REG_MEM_TIMING10, 0x00ff },
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- { GLAMO_REG_MEM_TIMING11, 0x0030 },
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- { GLAMO_REG_MEM_GEN, 0x3fff },
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- { GLAMO_REG_MEM_GEN, 0xafaf },
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- { GLAMO_REG_MEM_TIMING1, 0x0108 },
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- { GLAMO_REG_MEM_TIMING2, 0x0010 },
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- { GLAMO_REG_MEM_DRAM1, 0x0a00 },
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- { 0xfffe, 3 },
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- { GLAMO_REG_MEM_DRAM1, 0xe200 },
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- { 0xfffe, 1 },
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-};
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-
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-static const struct glamo_script regs_vram_8mb = {
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- { GLAMO_REG_CLOCK_MEMORY, 0x3aaa },
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- { 0xfffe, 50 },
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- { GLAMO_REG_CLOCK_MEMORY, 0x0aaa },
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- { 0xfffe, 3 },
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- { GLAMO_REG_MEM_POWER1, 0x0020 },
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- { 0x033a, 0x45cf },
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- { 0x033c, 0x4240 },
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- { 0x033e, 0x53e0 },
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- { 0x0340, 0x1401 },
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- { 0x0342, 0x0c44 },
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- { 0x0344, 0x1d0b },
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- { 0x0346, 0x25ac },
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- { 0x0348, 0x1953 },
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- { 0xfffe, 1 },
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- { GLAMO_REG_MEM_TYPE, 0x087a },
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- { GLAMO_REG_MEM_DRAM2, 0x01d6 },
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- { GLAMO_REG_MEM_TIMING8, 0x1060 },
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- { GLAMO_REG_MEM_TIMING9, 0x6067 },
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- { GLAMO_REG_MEM_TIMING10, 0x00ff },
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- { GLAMO_REG_MEM_TIMING11, 0x0030 },
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- { GLAMO_REG_MEM_GEN, 0x3fff },
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- { GLAMO_REG_MEM_GEN, 0xafaf },
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- { GLAMO_REG_MEM_TIMING1, 0x3108 },
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- { GLAMO_REG_MEM_TIMING2, 0x0010 },
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- { GLAMO_REG_MEM_DRAM1, 0x0a00 },
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- { 0xfffe, 3 },
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- { GLAMO_REG_MEM_DRAM1, 0xe200 },
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- { 0xfffe, 1 },
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-};
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-#endif
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enum glamo_power {
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GLAMO_POWER_ON,
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- GLAMO_POWER_STANDBY,
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GLAMO_POWER_SUSPEND,
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};
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static void glamo_power(struct glamo_core *glamo,
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enum glamo_power new_state)
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{
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+ int n;
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+
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spin_lock(&glamo->lock);
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dev_dbg(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
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@@ -836,37 +788,76 @@ static void glamo_power(struct glamo_core *glamo,
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while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
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;
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- /* enable memory clock and get it out of deep pwrdown */
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- __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
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- GLAMO_CLOCK_MEM_EN_MOCACLK, 0xffff);
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- __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM2,
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- GLAMO_MEM_DRAM2_DEEP_PWRDOWN, 0x0000);
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- __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM1,
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- GLAMO_MEM_DRAM1_SELF_REFRESH, 0x0000);
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-
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- glamo_run_script(glamo, glamo_resume_script,
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- ARRAY_SIZE(glamo_resume_script), 0);
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-
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- break;
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-
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- case GLAMO_POWER_STANDBY:
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- /* enable memory self-refresh */
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- __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM1,
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- GLAMO_MEM_DRAM1_SELF_REFRESH, 0xffff);
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- /* stop memory clock */
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- __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
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- GLAMO_CLOCK_MEM_EN_MOCACLK, 0x0000);
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- /* power down PLL2 and then PLL1 */
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- __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 0x2000, 0xffff);
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- __reg_set_bit_mask(glamo, GLAMO_REG_DFT_GEN5, 0x0001, 0xffff);
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+ /* Get memory out of deep powerdown */
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+
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
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+ (7 << 6) | /* tRC */
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+ (1 << 4) | /* tRP */
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+ (1 << 2) | /* tRCD */
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+ 2); /* CAS latency */
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+
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+ /* Stop self-refresh */
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+
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
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+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
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+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
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+ GLAMO_MEM_REFRESH_COUNT);
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
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+ GLAMO_MEM_DRAM1_EN_MODEREG_SET |
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+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
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+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
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+ GLAMO_MEM_REFRESH_COUNT);
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+
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+ /* re-enable clocks to memory */
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+
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+ __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY,
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+ GLAMO_CLOCK_MEM_EN_MOCACLK |
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+ GLAMO_CLOCK_MEM_EN_M1CLK |
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+ GLAMO_CLOCK_MEM_DG_M1CLK);
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+
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+ /* restore each engine that was up before suspend */
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+ for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
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+ if (glamo->engine_enabled_bitfield_suspend & (1 << n))
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+ __glamo_engine_enable(glamo, n);
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break;
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case GLAMO_POWER_SUSPEND:
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- __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM2,
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- GLAMO_MEM_DRAM2_DEEP_PWRDOWN, 0xffff);
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- /* stop memory clock */
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- __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
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- GLAMO_CLOCK_MEM_EN_MOCACLK, 0x0000);
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+ /* stash a copy of which engines were running */
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+ glamo->engine_enabled_bitfield_suspend =
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+ glamo->engine_enabled_bitfield;
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+
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+ /* take down each engine before we kill mem and pll */
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+ for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
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+ if (glamo->engine_enabled_bitfield & (1 << n))
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+ __glamo_engine_disable(glamo, n);
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+
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+ /* enable self-refresh */
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+
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
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+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
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+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
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+ GLAMO_MEM_DRAM1_SELF_REFRESH |
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+ GLAMO_MEM_REFRESH_COUNT);
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
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+ GLAMO_MEM_DRAM1_EN_MODEREG_SET |
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+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
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+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
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+ GLAMO_MEM_DRAM1_SELF_REFRESH |
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+ GLAMO_MEM_REFRESH_COUNT);
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+
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+ /* force RAM into deep powerdown */
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+
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+ __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
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+ GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
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+ (7 << 6) | /* tRC */
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+ (1 << 4) | /* tRP */
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+ (1 << 2) | /* tRCD */
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+ 2); /* CAS latency */
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+
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+ /* kill clocks to memory */
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+
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+ __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
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+
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/* power down PLL2 and then PLL1 */
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__reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 0x2000, 0xffff);
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__reg_set_bit_mask(glamo, GLAMO_REG_DFT_GEN5, 0x0001, 0xffff);
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@@ -1016,15 +1007,15 @@ static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
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char * name;
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};
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struct reg_range reg_range[] = {
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-/* { 0x0000, 0x200, "General" },
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- { 0x0200, 0x100, "Host Bus" },
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- { 0x0300, 0x100, "Memory" },
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- { 0x0400, 0x100, "Sensor" },
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+ { 0x0000, 0x76, "General" },
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+/* { 0x0200, 0x100, "Host Bus" },
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+*/ { 0x0300, 0x38, "Memory" },
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+/* { 0x0400, 0x100, "Sensor" },
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{ 0x0500, 0x300, "ISP" },
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{ 0x0800, 0x400, "JPEG" },
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{ 0x0c00, 0x500, "MPEG" },
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*/
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- { 0x1100, 0x400, "LCD" },
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+ { 0x1100, 0x88, "LCD" },
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/*
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{ 0x1500, 0x080, "MPU 0" },
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{ 0x1580, 0x080, "MPU 1" },
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@@ -1039,7 +1030,7 @@ static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
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for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
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n1 = 0;
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- end += sprintf(end, "\n%s\n\n", reg_range[r].name);
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+ end += sprintf(end, "\n%s\n", reg_range[r].name);
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for (n = reg_range[r].start;
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n < reg_range[r].start + reg_range[r].count; n += 2) {
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if (((n1++) & 7) == 0)
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diff --git a/drivers/mfd/glamo/glamo-core.h b/drivers/mfd/glamo/glamo-core.h
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index b1531b3..c89f810 100644
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--- a/drivers/mfd/glamo/glamo-core.h
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+++ b/drivers/mfd/glamo/glamo-core.h
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@@ -30,6 +30,8 @@ struct glamo_core {
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u_int16_t revision;
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spinlock_t lock;
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struct resume_dependency resume_dependency;
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+ u32 engine_enabled_bitfield;
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+ u32 engine_enabled_bitfield_suspend;
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};
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struct glamo_script {
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diff --git a/drivers/mfd/glamo/glamo-regs.h b/drivers/mfd/glamo/glamo-regs.h
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index 32411e3..2328b8a 100644
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--- a/drivers/mfd/glamo/glamo-regs.h
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+++ b/drivers/mfd/glamo/glamo-regs.h
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@@ -142,8 +142,12 @@ enum glamo_register_mem {
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#define GLAMO_MEM_TYPE_MASK 0x03
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enum glamo_reg_mem_dram1 {
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- GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),
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+ /* b0 - b10 == refresh period, 1 -> 2048 clocks */
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+ GLAMO_MEM_DRAM1_EN_GATE_CLK = (1 << 11),
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GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
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+ GLAMO_MEM_DRAM1_EN_GATE_CKE = (1 << 13),
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+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
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+ GLAMO_MEM_DRAM1_EN_MODEREG_SET = (1 << 15),
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};
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enum glamo_reg_mem_dram2 {
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--
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1.5.6.3
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