mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 15:39:18 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34651 3c298f89-4303-0410-b956-a3cf2f4a3e73
972 lines
29 KiB
Diff
972 lines
29 KiB
Diff
--- a/arch/mips/bcm47xx/nvram.c
|
|
+++ b/arch/mips/bcm47xx/nvram.c
|
|
@@ -43,8 +43,8 @@ static void early_nvram_init(void)
|
|
#ifdef CONFIG_BCM47XX_SSB
|
|
case BCM47XX_BUS_TYPE_SSB:
|
|
mcore_ssb = &bcm47xx_bus.ssb.mipscore;
|
|
- base = mcore_ssb->flash_window;
|
|
- lim = mcore_ssb->flash_window_size;
|
|
+ base = mcore_ssb->pflash.window;
|
|
+ lim = mcore_ssb->pflash.window_size;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_BCM47XX_BCMA
|
|
--- a/arch/mips/bcm47xx/wgt634u.c
|
|
+++ b/arch/mips/bcm47xx/wgt634u.c
|
|
@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
|
|
SSB_CHIPCO_IRQ_GPIO);
|
|
}
|
|
|
|
- wgt634u_flash_data.width = mcore->flash_buswidth;
|
|
- wgt634u_flash_resource.start = mcore->flash_window;
|
|
- wgt634u_flash_resource.end = mcore->flash_window
|
|
- + mcore->flash_window_size
|
|
+ wgt634u_flash_data.width = mcore->pflash.buswidth;
|
|
+ wgt634u_flash_resource.start = mcore->pflash.window;
|
|
+ wgt634u_flash_resource.end = mcore->pflash.window
|
|
+ + mcore->pflash.window_size
|
|
- 1;
|
|
return platform_add_devices(wgt634u_devices,
|
|
ARRAY_SIZE(wgt634u_devices));
|
|
--- a/drivers/bcma/bcma_private.h
|
|
+++ b/drivers/bcma/bcma_private.h
|
|
@@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma
|
|
#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
|
|
|
/* driver_chipcommon_pmu.c */
|
|
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
|
|
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
|
|
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
|
|
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
|
|
|
|
#ifdef CONFIG_BCMA_SFLASH
|
|
/* driver_chipcommon_sflash.c */
|
|
@@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo
|
|
/* driver_pci.c */
|
|
u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
|
|
|
|
+extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
|
|
+
|
|
#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
|
|
bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
|
|
void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
|
|
--- a/drivers/bcma/driver_chipcommon.c
|
|
+++ b/drivers/bcma/driver_chipcommon.c
|
|
@@ -4,12 +4,15 @@
|
|
*
|
|
* Copyright 2005, Broadcom Corporation
|
|
* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
|
|
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
|
*
|
|
* Licensed under the GNU/GPL. See COPYING for details.
|
|
*/
|
|
|
|
#include "bcma_private.h"
|
|
+#include <linux/bcm47xx_wdt.h>
|
|
#include <linux/export.h>
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/bcma/bcma.h>
|
|
|
|
static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
|
|
@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
|
|
return value;
|
|
}
|
|
|
|
-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
|
+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
- u32 leddc_on = 10;
|
|
- u32 leddc_off = 90;
|
|
+ if (cc->capabilities & BCMA_CC_CAP_PMU)
|
|
+ return bcma_pmu_get_alp_clock(cc);
|
|
|
|
- if (cc->setup_done)
|
|
+ return 20000000;
|
|
+}
|
|
+
|
|
+static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ u32 nb;
|
|
+
|
|
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
|
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
|
|
+ nb = 32;
|
|
+ else if (cc->core->id.rev < 26)
|
|
+ nb = 16;
|
|
+ else
|
|
+ nb = (cc->core->id.rev >= 37) ? 32 : 24;
|
|
+ } else {
|
|
+ nb = 28;
|
|
+ }
|
|
+ if (nb == 32)
|
|
+ return 0xffffffff;
|
|
+ else
|
|
+ return (1 << nb) - 1;
|
|
+}
|
|
+
|
|
+static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
|
+ u32 ticks)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
|
|
+
|
|
+ return bcma_chipco_watchdog_timer_set(cc, ticks);
|
|
+}
|
|
+
|
|
+static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
|
|
+ u32 ms)
|
|
+{
|
|
+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
|
|
+ u32 ticks;
|
|
+
|
|
+ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
|
|
+ return ticks / cc->ticks_per_ms;
|
|
+}
|
|
+
|
|
+static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
|
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
|
|
+ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
|
|
+ return bcma_chipco_get_alp_clock(cc) / 4000;
|
|
+ else
|
|
+ /* based on 32KHz ILP clock */
|
|
+ return 32;
|
|
+ } else {
|
|
+ return bcma_chipco_get_alp_clock(cc) / 1000;
|
|
+ }
|
|
+}
|
|
+
|
|
+int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcm47xx_wdt wdt = {};
|
|
+ struct platform_device *pdev;
|
|
+
|
|
+ wdt.driver_data = cc;
|
|
+ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
|
|
+ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
|
|
+ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
|
|
+
|
|
+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
|
|
+ cc->core->bus->num, &wdt,
|
|
+ sizeof(wdt));
|
|
+ if (IS_ERR(pdev))
|
|
+ return PTR_ERR(pdev);
|
|
+
|
|
+ cc->watchdog = pdev;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ if (cc->early_setup_done)
|
|
return;
|
|
|
|
if (cc->core->id.rev >= 11)
|
|
@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
|
|
if (cc->core->id.rev >= 35)
|
|
cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
|
|
|
|
+ if (cc->capabilities & BCMA_CC_CAP_PMU)
|
|
+ bcma_pmu_early_init(cc);
|
|
+
|
|
+ cc->early_setup_done = true;
|
|
+}
|
|
+
|
|
+void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ u32 leddc_on = 10;
|
|
+ u32 leddc_off = 90;
|
|
+
|
|
+ if (cc->setup_done)
|
|
+ return;
|
|
+
|
|
+ bcma_core_chipcommon_early_init(cc);
|
|
+
|
|
if (cc->core->id.rev >= 20) {
|
|
bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
|
|
bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
|
|
@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
|
|
((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
|
|
(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
|
|
}
|
|
+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
|
|
|
|
cc->setup_done = true;
|
|
}
|
|
|
|
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
|
|
-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
|
|
+u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
|
|
{
|
|
- /* instant NMI */
|
|
- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
|
|
+ u32 maxt;
|
|
+ enum bcma_clkmode clkmode;
|
|
+
|
|
+ maxt = bcma_chipco_watchdog_get_max_timer(cc);
|
|
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
|
+ if (ticks == 1)
|
|
+ ticks = 2;
|
|
+ else if (ticks > maxt)
|
|
+ ticks = maxt;
|
|
+ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
|
|
+ } else {
|
|
+ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
|
|
+ bcma_core_set_clockmode(cc->core, clkmode);
|
|
+ if (ticks > maxt)
|
|
+ ticks = maxt;
|
|
+ /* instant NMI */
|
|
+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
|
|
+ }
|
|
+ return ticks;
|
|
}
|
|
|
|
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
|
|
struct bcma_serial_port *ports = cc->serial_ports;
|
|
|
|
if (ccrev >= 11 && ccrev != 15) {
|
|
- /* Fixed ALP clock */
|
|
- baud_base = bcma_pmu_alp_clock(cc);
|
|
+ baud_base = bcma_chipco_get_alp_clock(cc);
|
|
if (ccrev >= 21) {
|
|
/* Turn off UART clock before switching clocksource. */
|
|
bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
|
--- a/drivers/bcma/driver_chipcommon_nflash.c
|
|
+++ b/drivers/bcma/driver_chipcommon_nflash.c
|
|
@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
|
|
}
|
|
|
|
cc->nflash.present = true;
|
|
+ if (cc->core->id.rev == 38 &&
|
|
+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
|
|
+ cc->nflash.boot = true;
|
|
|
|
/* Prepare platform device, but don't register it yet. It's too early,
|
|
* malloc (required by device_private_init) is not available yet. */
|
|
--- a/drivers/bcma/driver_chipcommon_pmu.c
|
|
+++ b/drivers/bcma/driver_chipcommon_pmu.c
|
|
@@ -144,7 +144,7 @@ static void bcma_pmu_workarounds(struct
|
|
}
|
|
}
|
|
|
|
-void bcma_pmu_init(struct bcma_drv_cc *cc)
|
|
+void bcma_pmu_early_init(struct bcma_drv_cc *cc)
|
|
{
|
|
u32 pmucap;
|
|
|
|
@@ -153,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
|
|
|
bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
|
|
cc->pmu.rev, pmucap);
|
|
+}
|
|
|
|
+void bcma_pmu_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
if (cc->pmu.rev == 1)
|
|
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
|
|
~BCMA_CC_PMU_CTL_NOILPONW);
|
|
@@ -165,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
|
bcma_pmu_workarounds(cc);
|
|
}
|
|
|
|
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
|
|
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
@@ -193,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
|
|
/* Find the output of the "m" pll divider given pll controls that start with
|
|
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
|
|
*/
|
|
-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
{
|
|
u32 tmp, div, ndiv, p1, p2, fc;
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
@@ -222,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
|
|
ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
|
|
|
|
/* Do calculation in Mhz */
|
|
- fc = bcma_pmu_alp_clock(cc) / 1000000;
|
|
+ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
|
|
fc = (p1 * ndiv * fc) / p2;
|
|
|
|
/* Return clock in Hertz */
|
|
return (fc / div) * 1000000;
|
|
}
|
|
|
|
-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
{
|
|
u32 tmp, ndiv, p1div, p2div;
|
|
u32 clock;
|
|
@@ -260,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
|
|
}
|
|
|
|
/* query bus clock frequency for PMU-enabled chipcommon */
|
|
-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
|
|
+static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
@@ -268,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(str
|
|
case BCMA_CHIP_ID_BCM4716:
|
|
case BCMA_CHIP_ID_BCM4748:
|
|
case BCMA_CHIP_ID_BCM47162:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM5356:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM5357:
|
|
case BCMA_CHIP_ID_BCM4749:
|
|
- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM4706:
|
|
- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
- BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
|
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
case BCMA_CHIP_ID_BCM53572:
|
|
return 75000000;
|
|
default:
|
|
- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
|
+ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
|
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
|
|
}
|
|
return BCMA_CC_PMU_HT_CLOCK;
|
|
}
|
|
|
|
/* query cpu clock frequency for PMU-enabled chipcommon */
|
|
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
|
|
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
|
|
{
|
|
struct bcma_bus *bus = cc->core->bus;
|
|
|
|
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
|
|
return 300000000;
|
|
|
|
+ /* New PMUs can have different clock for bus and CPU */
|
|
if (cc->pmu.rev >= 5) {
|
|
u32 pll;
|
|
switch (bus->chipinfo.id) {
|
|
case BCMA_CHIP_ID_BCM4706:
|
|
- return bcma_pmu_clock_bcm4706(cc,
|
|
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
|
BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
BCMA_CC_PMU5_MAINPLL_CPU);
|
|
case BCMA_CHIP_ID_BCM5356:
|
|
@@ -316,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
|
|
break;
|
|
}
|
|
|
|
- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
|
+ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
|
}
|
|
|
|
- return bcma_pmu_get_clockcontrol(cc);
|
|
+ /* On old PMUs CPU has the same clock as the bus */
|
|
+ return bcma_pmu_get_bus_clock(cc);
|
|
}
|
|
|
|
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
|
--- a/drivers/bcma/driver_chipcommon_sflash.c
|
|
+++ b/drivers/bcma/driver_chipcommon_sflash.c
|
|
@@ -12,7 +12,7 @@
|
|
|
|
static struct resource bcma_sflash_resource = {
|
|
.name = "bcma_sflash",
|
|
- .start = BCMA_SFLASH,
|
|
+ .start = BCMA_SOC_FLASH2,
|
|
.end = 0,
|
|
.flags = IORESOURCE_MEM | IORESOURCE_READONLY,
|
|
};
|
|
@@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
|
|
};
|
|
|
|
static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
|
|
- { "", 0x14, 0x10000, 32, },
|
|
+ { "M25P20", 0x11, 0x10000, 4, },
|
|
+ { "M25P40", 0x12, 0x10000, 8, },
|
|
+
|
|
+ { "M25P16", 0x14, 0x10000, 32, },
|
|
+ { "M25P32", 0x14, 0x10000, 64, },
|
|
+ { "M25P64", 0x16, 0x10000, 128, },
|
|
+ { "M25FL128", 0x17, 0x10000, 256, },
|
|
{ 0 },
|
|
};
|
|
|
|
static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
|
|
+ { "SST25WF512", 1, 0x1000, 16, },
|
|
+ { "SST25VF512", 0x48, 0x1000, 16, },
|
|
+ { "SST25WF010", 2, 0x1000, 32, },
|
|
+ { "SST25VF010", 0x49, 0x1000, 32, },
|
|
+ { "SST25WF020", 3, 0x1000, 64, },
|
|
+ { "SST25VF020", 0x43, 0x1000, 64, },
|
|
+ { "SST25WF040", 4, 0x1000, 128, },
|
|
+ { "SST25VF040", 0x44, 0x1000, 128, },
|
|
+ { "SST25VF040B", 0x8d, 0x1000, 128, },
|
|
+ { "SST25WF080", 5, 0x1000, 256, },
|
|
+ { "SST25VF080B", 0x8e, 0x1000, 256, },
|
|
+ { "SST25VF016", 0x41, 0x1000, 512, },
|
|
+ { "SST25VF032", 0x4a, 0x1000, 1024, },
|
|
+ { "SST25VF064", 0x4b, 0x1000, 2048, },
|
|
{ 0 },
|
|
};
|
|
|
|
static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
|
|
+ { "AT45DB011", 0xc, 256, 512, },
|
|
+ { "AT45DB021", 0x14, 256, 1024, },
|
|
+ { "AT45DB041", 0x1c, 256, 2048, },
|
|
+ { "AT45DB081", 0x24, 256, 4096, },
|
|
+ { "AT45DB161", 0x2c, 512, 4096, },
|
|
+ { "AT45DB321", 0x34, 512, 8192, },
|
|
+ { "AT45DB642", 0x3c, 1024, 8192, },
|
|
{ 0 },
|
|
};
|
|
|
|
@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
|
|
break;
|
|
}
|
|
break;
|
|
+ case 0x13:
|
|
+ return -ENOTSUPP;
|
|
default:
|
|
for (e = bcma_sflash_st_tbl; e->name; e++) {
|
|
if (e->id == id)
|
|
@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
- sflash->window = BCMA_SFLASH;
|
|
+ sflash->window = BCMA_SOC_FLASH2;
|
|
sflash->blocksize = e->blocksize;
|
|
sflash->numblocks = e->numblocks;
|
|
sflash->size = sflash->blocksize * sflash->numblocks;
|
|
--- a/drivers/bcma/driver_mips.c
|
|
+++ b/drivers/bcma/driver_mips.c
|
|
@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
|
|
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
|
|
~(1 << irqflag));
|
|
else
|
|
- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
|
|
|
|
/* assign the new one */
|
|
if (irq == 0) {
|
|
@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
|
|
struct bcma_bus *bus = mcore->core->bus;
|
|
|
|
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
|
|
- return bcma_pmu_get_clockcpu(&bus->drv_cc);
|
|
+ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
|
|
|
|
bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
|
|
return 0;
|
|
@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
|
|
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
|
|
{
|
|
struct bcma_bus *bus = mcore->core->bus;
|
|
+ struct bcma_drv_cc *cc = &bus->drv_cc;
|
|
|
|
- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
|
|
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
|
|
case BCMA_CC_FLASHT_STSER:
|
|
case BCMA_CC_FLASHT_ATSER:
|
|
bcma_debug(bus, "Found serial flash\n");
|
|
- bcma_sflash_init(&bus->drv_cc);
|
|
+ bcma_sflash_init(cc);
|
|
break;
|
|
case BCMA_CC_FLASHT_PARA:
|
|
bcma_debug(bus, "Found parallel flash\n");
|
|
- bus->drv_cc.pflash.window = 0x1c000000;
|
|
- bus->drv_cc.pflash.window_size = 0x02000000;
|
|
+ cc->pflash.present = true;
|
|
+ cc->pflash.window = BCMA_SOC_FLASH2;
|
|
+ cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
|
|
|
|
- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
|
|
+ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
|
|
BCMA_CC_FLASH_CFG_DS) == 0)
|
|
- bus->drv_cc.pflash.buswidth = 1;
|
|
+ cc->pflash.buswidth = 1;
|
|
else
|
|
- bus->drv_cc.pflash.buswidth = 2;
|
|
+ cc->pflash.buswidth = 2;
|
|
break;
|
|
default:
|
|
bcma_err(bus, "Flash type not supported\n");
|
|
}
|
|
|
|
- if (bus->drv_cc.core->id.rev == 38 ||
|
|
+ if (cc->core->id.rev == 38 ||
|
|
bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
|
|
- if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
|
|
+ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
|
|
bcma_debug(bus, "Found NAND flash\n");
|
|
- bcma_nflash_init(&bus->drv_cc);
|
|
+ bcma_nflash_init(cc);
|
|
}
|
|
}
|
|
}
|
|
|
|
+void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
|
|
+{
|
|
+ struct bcma_bus *bus = mcore->core->bus;
|
|
+
|
|
+ if (mcore->early_setup_done)
|
|
+ return;
|
|
+
|
|
+ bcma_chipco_serial_init(&bus->drv_cc);
|
|
+ bcma_core_mips_flash_detect(mcore);
|
|
+
|
|
+ mcore->early_setup_done = true;
|
|
+}
|
|
+
|
|
void bcma_core_mips_init(struct bcma_drv_mips *mcore)
|
|
{
|
|
struct bcma_bus *bus;
|
|
struct bcma_device *core;
|
|
bus = mcore->core->bus;
|
|
|
|
+ if (mcore->setup_done)
|
|
+ return;
|
|
+
|
|
bcma_info(bus, "Initializing MIPS core...\n");
|
|
|
|
- if (!mcore->setup_done)
|
|
- mcore->assigned_irqs = 1;
|
|
+ bcma_core_mips_early_init(mcore);
|
|
+
|
|
+ mcore->assigned_irqs = 1;
|
|
|
|
/* Assign IRQs to all cores on the bus */
|
|
list_for_each_entry(core, &bus->cores, list) {
|
|
@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
|
|
bcma_info(bus, "IRQ reconfiguration done\n");
|
|
bcma_core_mips_dump_irq(bus);
|
|
|
|
- if (mcore->setup_done)
|
|
- return;
|
|
-
|
|
- bcma_chipco_serial_init(&bus->drv_cc);
|
|
- bcma_core_mips_flash_detect(mcore);
|
|
mcore->setup_done = true;
|
|
}
|
|
--- a/drivers/bcma/driver_pci_host.c
|
|
+++ b/drivers/bcma/driver_pci_host.c
|
|
@@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
|
|
chipid_top != 0x5300)
|
|
return false;
|
|
|
|
- if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
- bcma_info(bus, "This PCI core is disabled and not working\n");
|
|
- return false;
|
|
- }
|
|
-
|
|
bcma_core_enable(pc->core, 0);
|
|
|
|
return !mips_busprobe32(tmp, pc->core->io_addr);
|
|
@@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
|
|
|
|
bcma_info(bus, "PCIEcore in host mode found\n");
|
|
|
|
+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
+ bcma_info(bus, "This PCIE core is disabled and not working\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
|
|
if (!pc_host) {
|
|
bcma_err(bus, "can not allocate memory");
|
|
@@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x100;
|
|
+ pc_host->io_resource.end = 0x47F;
|
|
pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
tmp | BCMA_SOC_PCI_MEM);
|
|
@@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x480;
|
|
+ pc_host->io_resource.end = 0x7FF;
|
|
pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
|
|
pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
@@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
|
|
static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
|
|
{
|
|
struct resource *res;
|
|
- int pos;
|
|
+ int pos, err;
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
/* This is not a device on the PCI-core bridge. */
|
|
@@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
|
|
|
|
for (pos = 0; pos < 6; pos++) {
|
|
res = &dev->resource[pos];
|
|
- if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
|
|
- pci_assign_resource(dev, pos);
|
|
+ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
|
|
+ err = pci_assign_resource(dev, pos);
|
|
+ if (err)
|
|
+ pr_err("PCI: Problem fixing up the addresses on %s\n",
|
|
+ pci_name(dev));
|
|
+ }
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
|
|
--- a/drivers/bcma/host_pci.c
|
|
+++ b/drivers/bcma/host_pci.c
|
|
@@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
|
|
pci_set_drvdata(dev, NULL);
|
|
}
|
|
|
|
-#ifdef CONFIG_PM
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
static int bcma_host_pci_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
@@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
|
|
bcma_host_pci_resume);
|
|
#define BCMA_PM_OPS (&bcma_pm_ops)
|
|
|
|
-#else /* CONFIG_PM */
|
|
+#else /* CONFIG_PM_SLEEP */
|
|
|
|
#define BCMA_PM_OPS NULL
|
|
|
|
-#endif /* CONFIG_PM */
|
|
+#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
|
|
--- a/drivers/bcma/main.c
|
|
+++ b/drivers/bcma/main.c
|
|
@@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_find_core);
|
|
|
|
+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
|
|
+ u8 unit)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->id.id == coreid && core->core_unit == unit)
|
|
+ return core;
|
|
+ }
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
static void bcma_release_core_dev(struct device *dev)
|
|
{
|
|
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
@@ -153,6 +165,12 @@ static int bcma_register_cores(struct bc
|
|
}
|
|
#endif
|
|
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
|
+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering watchdog driver\n");
|
|
+ }
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -165,6 +183,8 @@ static void bcma_unregister_cores(struct
|
|
if (core->dev_registered)
|
|
device_unregister(&core->dev);
|
|
}
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ platform_device_unregister(bus->drv_cc.watchdog);
|
|
}
|
|
|
|
int __devinit bcma_bus_register(struct bcma_bus *bus)
|
|
@@ -183,6 +203,20 @@ int __devinit bcma_bus_register(struct b
|
|
return -1;
|
|
}
|
|
|
|
+ /* Early init CC core */
|
|
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
+ if (core) {
|
|
+ bus->drv_cc.core = core;
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ /* Try to get SPROM */
|
|
+ err = bcma_sprom_get(bus);
|
|
+ if (err == -ENOENT) {
|
|
+ bcma_err(bus, "No SPROM available\n");
|
|
+ } else if (err)
|
|
+ bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
+
|
|
/* Init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
@@ -198,10 +232,17 @@ int __devinit bcma_bus_register(struct b
|
|
}
|
|
|
|
/* Init PCIE core */
|
|
- core = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
|
|
if (core) {
|
|
- bus->drv_pci.core = core;
|
|
- bcma_core_pci_init(&bus->drv_pci);
|
|
+ bus->drv_pci[0].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[0]);
|
|
+ }
|
|
+
|
|
+ /* Init PCIE core */
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
|
|
+ if (core) {
|
|
+ bus->drv_pci[1].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[1]);
|
|
}
|
|
|
|
/* Init GBIT MAC COMMON core */
|
|
@@ -211,13 +252,6 @@ int __devinit bcma_bus_register(struct b
|
|
bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
|
|
}
|
|
|
|
- /* Try to get SPROM */
|
|
- err = bcma_sprom_get(bus);
|
|
- if (err == -ENOENT) {
|
|
- bcma_err(bus, "No SPROM available\n");
|
|
- } else if (err)
|
|
- bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
-
|
|
/* Register found cores */
|
|
bcma_register_cores(bus);
|
|
|
|
@@ -275,18 +309,18 @@ int __init bcma_bus_early_register(struc
|
|
return -1;
|
|
}
|
|
|
|
- /* Init CC core */
|
|
+ /* Early init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
bus->drv_cc.core = core;
|
|
- bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
}
|
|
|
|
- /* Init MIPS core */
|
|
+ /* Early init MIPS core */
|
|
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
if (core) {
|
|
bus->drv_mips.core = core;
|
|
- bcma_core_mips_init(&bus->drv_mips);
|
|
+ bcma_core_mips_early_init(&bus->drv_mips);
|
|
}
|
|
|
|
bcma_info(bus, "Early bus registered\n");
|
|
--- a/drivers/bcma/sprom.c
|
|
+++ b/drivers/bcma/sprom.c
|
|
@@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
|
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
|
|
|
|
err = bcma_sprom_valid(sprom);
|
|
- if (err)
|
|
+ if (err) {
|
|
+ bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
|
|
+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
|
|
goto out;
|
|
+ }
|
|
|
|
bcma_sprom_extract_r8(bus, sprom);
|
|
|
|
--- a/include/linux/bcma/bcma.h
|
|
+++ b/include/linux/bcma/bcma.h
|
|
@@ -157,6 +157,7 @@ struct bcma_host_ops {
|
|
|
|
/* Chip IDs of SoCs */
|
|
#define BCMA_CHIP_ID_BCM4706 0x5300
|
|
+#define BCMA_PKG_ID_BCM4706L 1
|
|
#define BCMA_CHIP_ID_BCM4716 0x4716
|
|
#define BCMA_PKG_ID_BCM4716 8
|
|
#define BCMA_PKG_ID_BCM4717 9
|
|
@@ -166,7 +167,11 @@ struct bcma_host_ops {
|
|
#define BCMA_CHIP_ID_BCM4749 0x4749
|
|
#define BCMA_CHIP_ID_BCM5356 0x5356
|
|
#define BCMA_CHIP_ID_BCM5357 0x5357
|
|
+#define BCMA_PKG_ID_BCM5358 9
|
|
+#define BCMA_PKG_ID_BCM47186 10
|
|
+#define BCMA_PKG_ID_BCM5357 11
|
|
#define BCMA_CHIP_ID_BCM53572 53572
|
|
+#define BCMA_PKG_ID_BCM47188 9
|
|
|
|
struct bcma_device {
|
|
struct bcma_bus *bus;
|
|
@@ -251,7 +256,7 @@ struct bcma_bus {
|
|
u8 num;
|
|
|
|
struct bcma_drv_cc drv_cc;
|
|
- struct bcma_drv_pci drv_pci;
|
|
+ struct bcma_drv_pci drv_pci[2];
|
|
struct bcma_drv_mips drv_mips;
|
|
struct bcma_drv_gmac_cmn drv_gmac_cmn;
|
|
|
|
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
|
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
|
@@ -1,6 +1,8 @@
|
|
#ifndef LINUX_BCMA_DRIVER_CC_H_
|
|
#define LINUX_BCMA_DRIVER_CC_H_
|
|
|
|
+#include <linux/platform_device.h>
|
|
+
|
|
/** ChipCommon core registers. **/
|
|
#define BCMA_CC_ID 0x0000
|
|
#define BCMA_CC_ID_ID 0x0000FFFF
|
|
@@ -510,6 +512,7 @@ struct bcma_chipcommon_pmu {
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
struct bcma_pflash {
|
|
+ bool present;
|
|
u8 buswidth;
|
|
u32 window;
|
|
u32 window_size;
|
|
@@ -532,6 +535,7 @@ struct mtd_info;
|
|
|
|
struct bcma_nflash {
|
|
bool present;
|
|
+ bool boot; /* This is the flash the SoC boots from */
|
|
|
|
struct mtd_info *mtd;
|
|
};
|
|
@@ -552,6 +556,7 @@ struct bcma_drv_cc {
|
|
u32 capabilities;
|
|
u32 capabilities_ext;
|
|
u8 setup_done:1;
|
|
+ u8 early_setup_done:1;
|
|
/* Fast Powerup Delay constant */
|
|
u16 fast_pwrup_delay;
|
|
struct bcma_chipcommon_pmu pmu;
|
|
@@ -567,6 +572,8 @@ struct bcma_drv_cc {
|
|
int nr_serial_ports;
|
|
struct bcma_serial_port serial_ports[4];
|
|
#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
|
+ u32 ticks_per_ms;
|
|
+ struct platform_device *watchdog;
|
|
};
|
|
|
|
/* Register access */
|
|
@@ -583,14 +590,14 @@ struct bcma_drv_cc {
|
|
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
|
|
|
|
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
|
|
+extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
|
|
|
|
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
|
|
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
|
|
|
|
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
|
|
|
|
-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
|
|
- u32 ticks);
|
|
+extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
|
|
|
|
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
|
|
@@ -606,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
|
|
|
|
/* PMU support */
|
|
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
|
|
+extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
|
|
|
|
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
|
u32 value);
|
|
--- a/include/linux/bcma/bcma_driver_mips.h
|
|
+++ b/include/linux/bcma/bcma_driver_mips.h
|
|
@@ -35,13 +35,16 @@ struct bcma_device;
|
|
struct bcma_drv_mips {
|
|
struct bcma_device *core;
|
|
u8 setup_done:1;
|
|
+ u8 early_setup_done:1;
|
|
unsigned int assigned_irqs;
|
|
};
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
|
|
+extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
|
|
#else
|
|
static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
|
|
+static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
|
|
#endif
|
|
|
|
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
|
|
--- a/include/linux/bcma/bcma_regs.h
|
|
+++ b/include/linux/bcma/bcma_regs.h
|
|
@@ -85,6 +85,9 @@
|
|
* (2 ZettaBytes), high 32 bits
|
|
*/
|
|
|
|
-#define BCMA_SFLASH 0x1c000000
|
|
+#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
|
+#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
|
|
|
#endif /* LINUX_BCMA_REGS_H_ */
|
|
--- a/drivers/net/wireless/b43/main.c
|
|
+++ b/drivers/net/wireless/b43/main.c
|
|
@@ -4652,7 +4652,7 @@ static int b43_wireless_core_init(struct
|
|
switch (dev->dev->bus_type) {
|
|
#ifdef CONFIG_B43_BCMA
|
|
case B43_BUS_BCMA:
|
|
- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
|
|
+ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
|
|
dev->dev->bdev, true);
|
|
break;
|
|
#endif
|
|
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
|
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
|
@@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
|
|
sii = container_of(sih, struct si_info, pub);
|
|
|
|
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
|
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
|
|
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
|
|
}
|
|
|
|
/* Unconfigure and/or apply various WARs when going down */
|
|
@@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
|
|
sii = container_of(sih, struct si_info, pub);
|
|
|
|
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
|
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
|
|
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
|
|
}
|
|
|
|
/* Enable BT-COEX & Ex-PA for 4313 */
|
|
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
|
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
|
@@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
|
|
* Configure pci/pcmcia here instead of in brcms_c_attach()
|
|
* to allow mfg hotswap: down, hotswap (chip power cycle), up.
|
|
*/
|
|
- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
|
|
+ bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
|
|
true);
|
|
|
|
/*
|