mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16547 3c298f89-4303-0410-b956-a3cf2f4a3e73
1224 lines
40 KiB
Diff
1224 lines
40 KiB
Diff
From 5bac5f471fb1124c51a5811757c54174f6224e7e Mon Sep 17 00:00:00 2001
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From: Kurt Mahan <kmahan@freescale.com>
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Date: Wed, 12 Mar 2008 17:13:29 -0600
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Subject: [PATCH] Clean up FEC DMA driver.
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LTIBName: m547x-8x-fec-cleanup
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Signed-off-by: Kurt Mahan <kmahan@freescale.com>
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---
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drivers/net/fec/fec.c | 611 +++++++++++++++++++++---------------------------
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1 files changed, 267 insertions(+), 344 deletions(-)
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--- a/drivers/net/fec/fec.c
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+++ b/drivers/net/fec/fec.c
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@@ -4,7 +4,6 @@
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*
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* Code crunched to get it to work on 2.6.24 -- FEC cleanup coming
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* soon -- Kurt Mahan
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- *
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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@@ -44,42 +43,40 @@
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#undef FEC_2
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#endif
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-#define VERSION "0.13"
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+#define VERSION "0.20"
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MODULE_DESCRIPTION( "DMA Fast Ethernet Controller driver ver " VERSION);
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-// Private structure
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+/* fec private */
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struct fec_priv {
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struct net_device *netdev; /* owning net device */
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- void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; //Array of transmission buffers
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- MCD_bufDescFec *fecpriv_txdesc; // Array of transmission descriptors
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- volatile unsigned int fecpriv_current_tx; // Inex of the transmission descriptor that is used by DMA
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- volatile unsigned int fecpriv_next_tx; // Inex of the transmission descriptor that can be used for new data
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- unsigned int fecpriv_current_rx; // Index of the reception descriptor that is used by DMA
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- MCD_bufDescFec *fecpriv_rxdesc; // Array of reception descriptors
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-// unsigned char *fecpriv_rxbuf; // Address of reception buffers
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- struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; // Array of reception skb structure pointers
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- unsigned int fecpriv_initiator_rx; // Reception DMA initiator
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- unsigned int fecpriv_initiator_tx; // Transmission DMA initiator
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- int fecpriv_fec_rx_channel; // DMA reception channel
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- int fecpriv_fec_tx_channel; // DMA transmission channel
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- int fecpriv_rx_requestor; // DMA reception requestor
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- int fecpriv_tx_requestor; // DMA transmission requestor
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- void *fecpriv_interrupt_fec_rx_handler; // DMA reception handler
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- void *fecpriv_interrupt_fec_tx_handler; // DMA transmission handler
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- unsigned char *fecpriv_mac_addr; // Private copy of FEC address
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- struct net_device_stats fecpriv_stat; // Pointer to the statistical information
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+ void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */
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+ MCD_bufDescFec *fecpriv_txdesc; /* tx descriptor ptrs */
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+ volatile unsigned int fecpriv_current_tx; /* current tx desc index */
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+ volatile unsigned int fecpriv_next_tx; /* next tx desc index */
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+ unsigned int fecpriv_current_rx; /* current rx desc index */
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+ MCD_bufDescFec *fecpriv_rxdesc; /* rx descriptor ptrs */
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+ struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */
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+ unsigned int fecpriv_initiator_rx; /* rx dma initiator */
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+ unsigned int fecpriv_initiator_tx; /* tx dma initiator */
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+ int fecpriv_fec_rx_channel; /* rx dma channel */
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+ int fecpriv_fec_tx_channel; /* tx dma channel */
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+ int fecpriv_rx_requestor; /* rx dma requestor */
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+ int fecpriv_tx_requestor; /* tx dma requestor */
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+ void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */
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+ void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */
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+ unsigned char *fecpriv_mac_addr; /* private fec mac addr */
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+ struct net_device_stats fecpriv_stat; /* stats ptr */
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spinlock_t fecpriv_lock;
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int fecpriv_rxflag;
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struct tasklet_struct fecpriv_tasklet_reinit;
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- int index;
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+ int index; /* fec hw number */
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};
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struct net_device *fec_dev[FEC_MAX_PORTS];
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-// FEC functions
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+/* FEC functions */
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int __init fec_init(void);
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struct net_device_stats *fec_get_stat(struct net_device *dev);
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-
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int fec_open(struct net_device *dev);
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int fec_close(struct net_device *nd);
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int fec_tx(struct sk_buff *skb, struct net_device *dev);
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@@ -93,10 +90,12 @@ void fec_interrupt_fec_tx_handler_fec0(v
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void fec_interrupt_fec_rx_handler_fec0(void);
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void fec_interrupt_fec_reinit(unsigned long data);
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-unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 }; // Default address of FEC0
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+/* default fec0 address */
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+unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 };
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#ifdef FEC_2
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-unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 }; // Default address of FEC1
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+/* default fec1 address */
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+unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };
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#endif
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extern unsigned char uboot_enet0[];
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@@ -111,17 +110,18 @@ int __init fec_mac_setup0 (char *s);
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#ifdef FEC_2
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void fec_interrupt_fec_tx_handler_fec1(void);
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void fec_interrupt_fec_rx_handler_fec1(void);
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+#endif
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#ifndef MODULE
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int __init fec_mac_setup1 (char *s);
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#endif
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-#endif
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int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data);
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int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data);
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module_init(fec_init);
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/* module_exit(fec_cleanup); */
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+
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__setup("mac0=", fec_mac_setup0);
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#ifdef FEC_2
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@@ -140,7 +140,6 @@ int fec_enet_init(struct net_device *dev
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fp->index = index;
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fp->netdev = dev;
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fec_dev[ index ] = dev;
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-printk(KERN_INFO "FEI: index=%d\n", index);
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if (index == 0) {
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/* disable fec0 */
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@@ -175,8 +174,6 @@ printk(KERN_INFO "FEI: index=%d\n", inde
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/* rx descriptors */
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fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC0;
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-printk(KERN_INFO "FEI: txdesc=0x%p rxdesc=0x%p\n", fp->fecpriv_txdesc, fp->fecpriv_rxdesc);
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-
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/* mac addr */
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if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] ||
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uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) {
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@@ -229,8 +226,6 @@ printk(KERN_INFO "FEI: txdesc=0x%p rxde
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#endif
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}
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-printk(KERN_INFO "FEI: index=%d base_addr=0x%lx\n", index, dev->base_addr);
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-
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/* clear MIB */
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memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN);
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@@ -288,8 +283,7 @@ int __init fec_init(void)
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int err;
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DECLARE_MAC_BUF(mac);
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- printk(KERN_INFO "FEC ENET (DMA) Version .00\n");
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-
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+ printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION);
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for (i = 0; i < FEC_MAX_PORTS; i++) {
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dev = alloc_etherdev(sizeof(struct fec_priv));
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@@ -333,7 +327,6 @@ void fec_stop(struct net_device *dev)
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*
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* RETURNS: If no error occurs, this function returns zero.
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*************************************************************************/
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-
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int fec_open(struct net_device *dev)
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{
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struct fec_priv *fp = netdev_priv(dev);
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@@ -343,13 +336,10 @@ int fec_open(struct net_device *dev)
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int channel;
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int error_code = -EBUSY;
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-printk(KERN_INFO "FECOPEN: index=%d\n", fp->index);
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-
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- //Receive the DMA channels
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+ /* Receive the DMA channels */
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channel = dma_set_channel_fec(fp->fecpriv_rx_requestor);
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- if (channel == -1)
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- {
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+ if (channel == -1) {
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printk("Dma channel cannot be reserved\n");
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goto ERRORS;
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}
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@@ -360,60 +350,54 @@ printk(KERN_INFO "FECOPEN: index=%d\n",
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channel = dma_set_channel_fec(fp->fecpriv_tx_requestor);
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- if (channel == -1)
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- {
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+ if (channel == -1) {
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printk("Dma channel cannot be reserved\n");
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goto ERRORS;
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}
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-printk(KERN_INFO "FECOPEN2\n");
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fp->fecpriv_fec_tx_channel = channel;
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dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler);
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- // init tasklet for controller reinitialization
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+ /* init tasklet for controller reinitialization */
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tasklet_init(&fp->fecpriv_tasklet_reinit, fec_interrupt_fec_reinit, (unsigned long) dev);
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-printk(KERN_INFO "FECOPEN3\n");
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- // Reset FIFOs
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+ /* Reset FIFOs */
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FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL;
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FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
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- // Reset and disable FEC
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+ /* Reset and disable FEC */
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FEC_ECR(base_addr) = FEC_ECR_RESET;
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- // Wait
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udelay(10);
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- // Clear all events
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+ /* Clear all events */
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FEC_EIR(base_addr) = FEC_EIR_CLEAR;
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- // Reset FIFO status
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+ /* Reset FIFO status */
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FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK;
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FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK;
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-#if 0
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-/* JKM -- move into HW init */
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- // Copy the default address to the device structure
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- memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
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-#endif
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+ /* Set the default address */
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+ FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
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+ (fp->fecpriv_mac_addr[1] << 16) |
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+ (fp->fecpriv_mac_addr[2] << 8) |
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+ fp->fecpriv_mac_addr[3];
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+ FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
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+ (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
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- // Set the default address
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- FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
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- FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
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-
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- // Reset the group address descriptor
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+ /* Reset the group address descriptor */
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FEC_GALR(base_addr) = 0x00000000;
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FEC_GAUR(base_addr) = 0x00000000;
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- // Reset the individual address descriptor
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+ /* Reset the individual address descriptor */
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FEC_IALR(base_addr) = 0x00000000;
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FEC_IAUR(base_addr) = 0x00000000;
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- // Set the receive control register
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+ /* Set the receive control register */
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FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII;
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- // Set the receive FIFO control register
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+ /* Set the receive FIFO control register */
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// FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;
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FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR
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| (FEC_FECRFCR_MSK // disable all but ...
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@@ -422,10 +406,10 @@ printk(KERN_INFO "FECOPEN3\n");
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// & ~FEC_FECRFCR_UF // enable FIFO underflow
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);
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- //Set the receive FIFO alarm register
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+ /* Set the receive FIFO alarm register */
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FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM;
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- // Set the transmit FIFO control register
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+ /* Set the transmit FIFO control register */
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// FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;
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FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR
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| (FEC_FECTFCR_MSK // disable all but ...
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@@ -434,16 +418,16 @@ printk(KERN_INFO "FECOPEN3\n");
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// & ~FEC_FECTFCR_UF // enable FIFO underflow
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& ~FEC_FECTFCR_OF); // enable FIFO overflow
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- //Set the transmit FIFO alarm register
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+ /* Set the transmit FIFO alarm register */
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FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM;
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- // Set the Tx FIFO watermark
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+ /* Set the Tx FIFO watermark */
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FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK;
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- // Enable the transmitter to append the CRC
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+ /* Enable the transmitter to append the CRC */
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FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC;
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- // Enable the ethernet interrupts
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+ /* Enable the ethernet interrupts */
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// FEC_EIMR(base_addr) = FEC_EIMR_MASK;
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FEC_EIMR(base_addr) = FEC_EIMR_DISABLE
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| FEC_EIR_LC
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@@ -453,9 +437,16 @@ printk(KERN_INFO "FECOPEN3\n");
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| FEC_EIR_XFERR
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| FEC_EIR_RFERR
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;
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-printk(KERN_INFO "FECOPEN4\n");
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-#ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
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+/*
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+ * JKM --
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+ *
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+ * There's a problem with the PHY initialization code --
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+ * for now assume uboot left it in an initialized state.
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+ */
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+// printk(KERN_INFO "FECOPEN: starting auto-negotiation\n");
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+// #ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
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+#if 0
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if ((error_code = init_transceiver(base_addr, &fduplex)) != 0)
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{
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printk("Initialization of the transceiver is failed\n");
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@@ -464,25 +455,24 @@ printk(KERN_INFO "FECOPEN4\n");
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#else
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fduplex = 1;
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#endif
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-printk(KERN_INFO "FECOPEN5\n");
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+// printk(KERN_INFO "FECOPEN: done with auto-negotiation\n");
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if (fduplex)
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- // Enable the full duplex mode
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+ /* Enable the full duplex mode */
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FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC;
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else
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- // Disable reception of frames while transmitting
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+ /* Disable reception of frames while transmitting */
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FEC_RCR(base_addr) |= FEC_RCR_DRT;
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- // Enable MIB
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+ /* Enable MIB */
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FEC_MIBC(base_addr) = FEC_MIBC_ENABLE;
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- // Enable FEC
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+ /* Enable FEC */
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FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
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- // Initialize transmission descriptors and start DMA for the transmission
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+ /* Initialize tx descriptors and start DMA for the transmission */
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for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
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fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
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-printk(KERN_INFO "FECOPEN6\n");
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fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
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@@ -494,31 +484,27 @@ printk(KERN_INFO "FECOPEN6\n");
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FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
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MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
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- // Initialize reception descriptors and start DMA for the reception
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- for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
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- {
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+ /* Initialize rx descriptors and start DMA for the reception */
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+ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
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fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA);
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- if (!fp->askb_rx[i])
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- {
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- fp->fecpriv_rxdesc[i].dataPointer = 0;
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- fp->fecpriv_rxdesc[i].statCtrl = 0;
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- fp->fecpriv_rxdesc[i].length = 0;
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+ if (!fp->askb_rx[i]) {
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+ fp->fecpriv_rxdesc[i].dataPointer = 0;
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+ fp->fecpriv_rxdesc[i].statCtrl = 0;
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+ fp->fecpriv_rxdesc[i].length = 0;
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}
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- else
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- {
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- skb_reserve(fp->askb_rx[i], 16);
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+ else {
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+ skb_reserve(fp->askb_rx[i], 16);
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fp->askb_rx[i]->dev = dev;
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- fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
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- fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
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- fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
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- }
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+ fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
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+ fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
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+ fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
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+ }
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}
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-printk(KERN_INFO "FECOPEN7\n");
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fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
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fp->fecpriv_current_rx = 0;
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- // flush entire data cache before restarting the DMA
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+ /* flush entire data cache before restarting the DMA */
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#if 0
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/* JKM -- currently running with cache turned off */
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DcacheFlushInvalidate();
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@@ -531,31 +517,24 @@ printk(KERN_INFO "FECOPEN7\n");
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MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
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netif_start_queue(dev);
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-
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-// MOD_INC_USE_COUNT;
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-printk(KERN_INFO "FECOPEN: finished\n");
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-
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return 0;
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|
|
ERRORS:
|
|
|
|
- // Remove the channels and return with the error code
|
|
- if (fp->fecpriv_fec_rx_channel != -1)
|
|
- {
|
|
+ /* Remove the channels and return with the error code */
|
|
+ if (fp->fecpriv_fec_rx_channel != -1) {
|
|
dma_disconnect(fp->fecpriv_fec_rx_channel);
|
|
dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
|
|
fp->fecpriv_fec_rx_channel = -1;
|
|
}
|
|
|
|
- if (fp->fecpriv_fec_tx_channel != -1)
|
|
- {
|
|
+ if (fp->fecpriv_fec_tx_channel != -1) {
|
|
dma_disconnect(fp->fecpriv_fec_tx_channel);
|
|
dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
|
|
fp->fecpriv_fec_tx_channel = -1;
|
|
}
|
|
|
|
return error_code;
|
|
-
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -568,31 +547,26 @@ ERRORS:
|
|
*************************************************************************/
|
|
int fec_close(struct net_device *dev)
|
|
{
|
|
- //Receive the pointer to the private structure
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
-
|
|
- // Receive the base address
|
|
unsigned long base_addr = (unsigned long) dev->base_addr;
|
|
-
|
|
unsigned long time;
|
|
-
|
|
int i;
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
- // Perform the graceful stop
|
|
+ /* Perform the graceful stop */
|
|
FEC_TCR(base_addr) |= FEC_TCR_GTS;
|
|
|
|
time = jiffies;
|
|
|
|
- // Wait for the graceful stop
|
|
+ /* Wait for the graceful stop */
|
|
while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < FEC_GR_TIMEOUT * HZ)
|
|
schedule();
|
|
|
|
- // Disable FEC
|
|
+ /* Disable FEC */
|
|
FEC_ECR(base_addr) = FEC_ECR_DISABLE;
|
|
|
|
- // Reset the DMA channels
|
|
+ /* Reset the DMA channels */
|
|
spin_lock_irq(&fp->fecpriv_lock);
|
|
MCD_killDma(fp->fecpriv_fec_tx_channel);
|
|
spin_unlock_irq(&fp->fecpriv_lock);
|
|
@@ -600,12 +574,12 @@ int fec_close(struct net_device *dev)
|
|
dma_disconnect(fp->fecpriv_fec_tx_channel);
|
|
fp->fecpriv_fec_tx_channel = -1;
|
|
|
|
- for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
|
|
- if (fp->fecpriv_txbuf[i])
|
|
- {
|
|
+ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
|
|
+ if (fp->fecpriv_txbuf[i]) {
|
|
kfree(fp->fecpriv_txbuf[i]);
|
|
fp->fecpriv_txbuf[i] = NULL;
|
|
}
|
|
+ }
|
|
|
|
spin_lock_irq(&fp->fecpriv_lock);
|
|
MCD_killDma(fp->fecpriv_fec_rx_channel);
|
|
@@ -615,15 +589,12 @@ int fec_close(struct net_device *dev)
|
|
dma_disconnect(fp->fecpriv_fec_rx_channel);
|
|
fp->fecpriv_fec_rx_channel = -1;
|
|
|
|
- for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
|
|
- {
|
|
- if (fp->askb_rx[i])
|
|
- {
|
|
- kfree_skb(fp->askb_rx[i]);
|
|
- fp->askb_rx[i] = NULL;
|
|
- }
|
|
+ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
|
|
+ if (fp->askb_rx[i]) {
|
|
+ kfree_skb(fp->askb_rx[i]);
|
|
+ fp->askb_rx[i] = NULL;
|
|
+ }
|
|
}
|
|
-// MOD_DEC_USE_COUNT;
|
|
|
|
return 0;
|
|
}
|
|
@@ -635,14 +606,10 @@ int fec_close(struct net_device *dev)
|
|
*************************************************************************/
|
|
struct net_device_stats * fec_get_stat(struct net_device *dev)
|
|
{
|
|
-
|
|
- //Receive the pointer to the private structure
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
-
|
|
- // Receive the base address
|
|
unsigned long base_addr = dev->base_addr;
|
|
|
|
- // Receive the statistical information
|
|
+ /* Receive the statistical information */
|
|
fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr);
|
|
fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr);
|
|
fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr);
|
|
@@ -651,7 +618,10 @@ struct net_device_stats * fec_get_stat(s
|
|
fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr);
|
|
fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr);
|
|
|
|
- fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) + FECSTAT_RMON_R_OVERSIZE(base_addr) + FECSTAT_RMON_R_FRAG(base_addr) + FECSTAT_RMON_R_JAB(base_addr);
|
|
+ fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) +
|
|
+ FECSTAT_RMON_R_OVERSIZE(base_addr) +
|
|
+ FECSTAT_RMON_R_FRAG(base_addr) +
|
|
+ FECSTAT_RMON_R_JAB(base_addr);
|
|
fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr);
|
|
fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr);
|
|
fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr);
|
|
@@ -660,9 +630,18 @@ struct net_device_stats * fec_get_stat(s
|
|
fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr);
|
|
fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr);
|
|
|
|
- // I hope that one frame doesn't have more than one error
|
|
- fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors + fp->fecpriv_stat.rx_crc_errors + fp->fecpriv_stat.rx_frame_errors + fp->fecpriv_stat.rx_over_errors + fp->fecpriv_stat.rx_dropped;
|
|
- fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors + fp->fecpriv_stat.tx_fifo_errors + fp->fecpriv_stat.tx_window_errors + fp->fecpriv_stat.tx_aborted_errors + fp->fecpriv_stat.tx_heartbeat_errors + fp->fecpriv_stat.tx_dropped;
|
|
+ /* I hope that one frame doesn't have more than one error */
|
|
+ fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors +
|
|
+ fp->fecpriv_stat.rx_crc_errors +
|
|
+ fp->fecpriv_stat.rx_frame_errors +
|
|
+ fp->fecpriv_stat.rx_over_errors +
|
|
+ fp->fecpriv_stat.rx_dropped;
|
|
+ fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors +
|
|
+ fp->fecpriv_stat.tx_fifo_errors +
|
|
+ fp->fecpriv_stat.tx_window_errors +
|
|
+ fp->fecpriv_stat.tx_aborted_errors +
|
|
+ fp->fecpriv_stat.tx_heartbeat_errors +
|
|
+ fp->fecpriv_stat.tx_dropped;
|
|
|
|
return &fp->fecpriv_stat;
|
|
}
|
|
@@ -674,59 +653,47 @@ struct net_device_stats * fec_get_stat(s
|
|
*************************************************************************/
|
|
void fec_set_multicast_list(struct net_device *dev)
|
|
{
|
|
- // Pointer to the address list
|
|
struct dev_mc_list *dmi;
|
|
-
|
|
unsigned int crc, data;
|
|
int i, j, k;
|
|
-
|
|
- // Receive the base address
|
|
unsigned long base_addr = (unsigned long) dev->base_addr;
|
|
|
|
- if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI)
|
|
- {
|
|
- // Allow all incoming frames
|
|
+ if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) {
|
|
+ /* Allow all incoming frames */
|
|
FEC_GALR(base_addr) = 0xFFFFFFFF;
|
|
FEC_GAUR(base_addr) = 0xFFFFFFFF;
|
|
return;
|
|
}
|
|
- // Reset the group address register
|
|
+
|
|
+ /* Reset the group address register */
|
|
FEC_GALR(base_addr) = 0x00000000;
|
|
FEC_GAUR(base_addr) = 0x00000000;
|
|
|
|
- // Process all addresses
|
|
- for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next)
|
|
- {
|
|
- // Processing must be only for the group addresses
|
|
+ /* Process all addresses */
|
|
+ for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next) {
|
|
+ /* Processing must be only for the group addresses */
|
|
if (!(dmi->dmi_addr[0] & 1))
|
|
continue;
|
|
|
|
- // Calculate crc value for the current address
|
|
+ /* Calculate crc value for the current address */
|
|
crc = 0xFFFFFFFF;
|
|
- for (j = 0; j < dmi->dmi_addrlen; j++)
|
|
- {
|
|
-
|
|
- for (k = 0, data = dmi->dmi_addr[j]; k < 8; k++, data >>= 1)
|
|
- {
|
|
+ for (j = 0; j < dmi->dmi_addrlen; j++) {
|
|
+ for (k = 0, data = dmi->dmi_addr[j]; k < 8; k++, data >>= 1) {
|
|
if ((crc ^ data) & 1)
|
|
crc = (crc >> 1) ^ FEC_CRCPOL;
|
|
else
|
|
crc >>= 1;
|
|
-
|
|
}
|
|
-
|
|
}
|
|
|
|
- // Add this value
|
|
+ /* Add this value */
|
|
crc >>= 26;
|
|
crc &= 0x3F;
|
|
if (crc > 31)
|
|
FEC_GAUR(base_addr) |= 0x1 << (crc - 32);
|
|
else
|
|
FEC_GALR(base_addr) |= 0x1 << crc;
|
|
-
|
|
}
|
|
-
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -736,26 +703,27 @@ void fec_set_multicast_list(struct net_d
|
|
*************************************************************************/
|
|
int fec_set_mac_address(struct net_device *dev, void *p)
|
|
{
|
|
- //Receive the pointer to the private structure
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
-
|
|
- // Receive the base address
|
|
unsigned long base_addr = (unsigned long) dev->base_addr;
|
|
-
|
|
struct sockaddr *addr = p;
|
|
|
|
if (netif_running(dev))
|
|
return -EBUSY;
|
|
|
|
- // Copy a new address to the device structure
|
|
+ /* Copy a new address to the device structure */
|
|
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
|
|
|
- // Copy a new address to the private structure
|
|
+ /* Copy a new address to the private structure */
|
|
memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6);
|
|
|
|
- // Set the address to the registers
|
|
- FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
|
|
- FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
|
|
+ /* Set the address to the registers */
|
|
+ FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
|
|
+ (fp->fecpriv_mac_addr[1] << 16) |
|
|
+ (fp->fecpriv_mac_addr[2] << 8) |
|
|
+ fp->fecpriv_mac_addr[3];
|
|
+ FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
|
|
+ (fp->fecpriv_mac_addr[5] << 16) |
|
|
+ 0x8808;
|
|
|
|
return 0;
|
|
}
|
|
@@ -769,27 +737,24 @@ int fec_set_mac_address(struct net_devic
|
|
*************************************************************************/
|
|
int fec_tx(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
-
|
|
- //Receive the pointer to the private structure
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
-
|
|
void *data, *data_aligned;
|
|
int offset;
|
|
|
|
data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
|
|
|
|
- if (!data)
|
|
- {
|
|
+ if (!data) {
|
|
fp->fecpriv_stat.tx_dropped++;
|
|
dev_kfree_skb(skb);
|
|
return 0;
|
|
}
|
|
|
|
- offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) - (unsigned long)virt_to_phys(data);
|
|
+ offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) -
|
|
+ (unsigned long)virt_to_phys(data);
|
|
data_aligned = (void*)((unsigned long)data + offset);
|
|
memcpy(data_aligned, skb->data, skb->len);
|
|
|
|
- // flush data cache before initializing the descriptor and starting DMA
|
|
+ /* flush data cache before initializing the descriptor and starting DMA */
|
|
#if 0
|
|
/* JKM -- currently running with cache turned off */
|
|
DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(data_aligned), skb->len);
|
|
@@ -797,7 +762,7 @@ int fec_tx(struct sk_buff *skb, struct n
|
|
|
|
spin_lock_irq(&fp->fecpriv_lock);
|
|
|
|
- // Initialize the descriptor
|
|
+ /* Initialize the descriptor */
|
|
fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data;
|
|
fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer = (unsigned int) virt_to_phys(data_aligned);
|
|
fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len;
|
|
@@ -809,7 +774,7 @@ int fec_tx(struct sk_buff *skb, struct n
|
|
|
|
spin_unlock_irq(&fp->fecpriv_lock);
|
|
|
|
- // Tell the DMA to continue the transmission
|
|
+ /* Tell the DMA to continue the transmission */
|
|
MCD_continDma(fp->fecpriv_fec_tx_channel);
|
|
|
|
dev_kfree_skb(skb);
|
|
@@ -835,14 +800,10 @@ void fec_tx_timeout(struct net_device *d
|
|
|
|
spin_lock_irq(&fp->fecpriv_lock);
|
|
MCD_killDma(fp->fecpriv_fec_tx_channel);
|
|
- for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
|
|
- {
|
|
- if (fp->fecpriv_txbuf[i])
|
|
- {
|
|
-
|
|
+ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
|
|
+ if (fp->fecpriv_txbuf[i]) {
|
|
kfree(fp->fecpriv_txbuf[i]);
|
|
fp->fecpriv_txbuf[i] = NULL;
|
|
-
|
|
}
|
|
fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
|
|
}
|
|
@@ -850,14 +811,14 @@ void fec_tx_timeout(struct net_device *d
|
|
|
|
fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
|
|
|
|
- // Reset FIFOs
|
|
+ /* Reset FIFOs */
|
|
FEC_FECFRST(base_addr) |= FEC_SW_RST;
|
|
FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
|
|
|
|
- // Reset and disable FEC
|
|
+ /* Reset and disable FEC */
|
|
// FEC_ECR(base_addr) = FEC_ECR_RESET;
|
|
|
|
- // Enable FEC
|
|
+ /* Enable FEC */
|
|
FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
|
|
|
|
MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
|
|
@@ -883,23 +844,22 @@ int fec_read_mii(unsigned int base_addr,
|
|
{
|
|
unsigned long time;
|
|
|
|
- // Clear the MII interrupt bit
|
|
+ /* Clear the MII interrupt bit */
|
|
FEC_EIR(base_addr) = FEC_EIR_MII;
|
|
|
|
- // Write to the MII management frame register
|
|
+ /* Write to the MII management frame register */
|
|
FEC_MMFR(base_addr) = FEC_MMFR_READ | (pa << 23) | (ra << 18);
|
|
|
|
time = jiffies;
|
|
|
|
- // Wait for the reading
|
|
- while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
|
|
- {
|
|
+ /* Wait for the reading */
|
|
+ while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
|
|
if (jiffies - time > FEC_MII_TIMEOUT * HZ)
|
|
return -ETIME;
|
|
schedule();
|
|
}
|
|
|
|
- // Clear the MII interrupt bit
|
|
+ /* Clear the MII interrupt bit */
|
|
FEC_EIR(base_addr) = FEC_EIR_MII;
|
|
|
|
*data = FEC_MMFR(base_addr) & 0x0000FFFF;
|
|
@@ -918,25 +878,22 @@ int fec_write_mii(unsigned int base_addr
|
|
{
|
|
unsigned long time;
|
|
|
|
- // Clear the MII interrupt bit
|
|
+ /* Clear the MII interrupt bit */
|
|
FEC_EIR(base_addr) = FEC_EIR_MII;
|
|
|
|
- // Write to the MII management frame register
|
|
+ /* Write to the MII management frame register */
|
|
FEC_MMFR(base_addr) = FEC_MMFR_WRITE | (pa << 23) | (ra << 18) | data;
|
|
|
|
time = jiffies;
|
|
|
|
- // Wait for the writing
|
|
-
|
|
- while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
|
|
- {
|
|
+ /* Wait for the writing */
|
|
+ while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
|
|
if (jiffies - time > FEC_MII_TIMEOUT * HZ)
|
|
return -ETIME;
|
|
-
|
|
schedule();
|
|
}
|
|
|
|
- // Clear the MII interrupt bit
|
|
+ /* Clear the MII interrupt bit */
|
|
FEC_EIR(base_addr) = FEC_EIR_MII;
|
|
|
|
return 0;
|
|
@@ -953,27 +910,24 @@ void fec_interrupt_fec_tx_handler(struct
|
|
{
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
|
|
- //Release the socket buffer
|
|
- if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
|
|
- {
|
|
+ /* Release the socket buffer */
|
|
+ if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
|
|
kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
|
|
fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
|
|
}
|
|
fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK;
|
|
|
|
- if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE)
|
|
- for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK)
|
|
- {
|
|
- if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
|
|
- {
|
|
+ if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) {
|
|
+ for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK) {
|
|
+ if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
|
|
kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
|
|
fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
|
|
}
|
|
}
|
|
+ }
|
|
|
|
if (netif_queue_stopped(dev))
|
|
netif_wake_queue(dev);
|
|
-
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -1008,49 +962,41 @@ void fec_interrupt_fec_rx_handler(struct
|
|
}
|
|
}
|
|
*/
|
|
- for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK)
|
|
- {
|
|
+ for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK) {
|
|
if( (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length <= FEC_MAXBUF_SIZE) &&
|
|
- (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) // --tym--
|
|
- {
|
|
+ (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) { /* --tym-- */
|
|
skb = fp->askb_rx[fp->fecpriv_current_rx];
|
|
if (!skb)
|
|
- {
|
|
- fp->fecpriv_stat.rx_dropped++;
|
|
- }
|
|
- else
|
|
- {
|
|
- // flush data cache before initializing the descriptor and starting DMA
|
|
+ fp->fecpriv_stat.rx_dropped++;
|
|
+ else {
|
|
+ /* flush data cache before initializing the descriptor and starting DMA */
|
|
// DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), fp->askb_rx[fp->fecpriv_current_rx]->len);
|
|
|
|
skb_put(skb, fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length - 4);
|
|
-// skb->dev = dev;
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
netif_rx(skb);
|
|
- }
|
|
- fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
|
|
- // allocate new skbuff
|
|
+ }
|
|
+ fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
|
|
+ /* allocate new skbuff */
|
|
fp->askb_rx[fp->fecpriv_current_rx] = alloc_skb(FEC_MAXBUF_SIZE + 16, /*GFP_ATOMIC |*/ GFP_DMA);
|
|
- if (!fp->askb_rx[fp->fecpriv_current_rx])
|
|
- {
|
|
- fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
|
|
- fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
|
|
- fp->fecpriv_stat.rx_dropped++;
|
|
- }
|
|
- else
|
|
- {
|
|
- skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
|
|
- fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
|
|
+ if (!fp->askb_rx[fp->fecpriv_current_rx]) {
|
|
+ fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
|
|
+ fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
|
|
+ fp->fecpriv_stat.rx_dropped++;
|
|
+ }
|
|
+ else {
|
|
+ skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
|
|
+ fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
|
|
|
|
- // flush data cache before initializing the descriptor and starting DMA
|
|
+ /* flush data cache before initializing the descriptor and starting DMA */
|
|
#if 0
|
|
/* JKM -- currently running with cache turned off */
|
|
- DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
|
|
+ DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
|
|
#endif
|
|
|
|
fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail);
|
|
fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = FEC_MAXBUF_SIZE;
|
|
- fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
|
|
+ fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
|
|
|
|
// flush data cache before initializing the descriptor and starting DMA
|
|
// DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
|
|
@@ -1059,11 +1005,10 @@ void fec_interrupt_fec_rx_handler(struct
|
|
|
|
}
|
|
|
|
- // Tell the DMA to continue the reception
|
|
+ /* Tell the DMA to continue the reception */
|
|
MCD_continDma(fp->fecpriv_fec_rx_channel);
|
|
|
|
fp->fecpriv_rxflag = 0;
|
|
-
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -1080,76 +1025,70 @@ irqreturn_t fec_interrupt_handler(int ir
|
|
unsigned long base_addr = (unsigned long) dev->base_addr;
|
|
unsigned long events;
|
|
|
|
- // Read and clear the events
|
|
+ /* Read and clear the events */
|
|
events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
|
|
|
|
- if (events & FEC_EIR_HBERR)
|
|
- {
|
|
+ if (events & FEC_EIR_HBERR) {
|
|
fp->fecpriv_stat.tx_heartbeat_errors++;
|
|
- FEC_EIR(base_addr) = FEC_EIR_HBERR;
|
|
+ FEC_EIR(base_addr) = FEC_EIR_HBERR;
|
|
}
|
|
|
|
- // receive/transmit FIFO error
|
|
- if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0))
|
|
- {
|
|
- // kill DMA receive channel
|
|
- MCD_killDma (fp->fecpriv_fec_rx_channel);
|
|
- // kill running transmission by DMA
|
|
- MCD_killDma (fp->fecpriv_fec_tx_channel);
|
|
-
|
|
- // Reset FIFOs
|
|
- FEC_FECFRST(base_addr) |= FEC_SW_RST;
|
|
- FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
|
|
-
|
|
- // reset receive FIFO status register
|
|
- FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE
|
|
- | FEC_FECRFSR_RXW
|
|
- | FEC_FECRFSR_UF;
|
|
-
|
|
- // reset transmit FIFO status register
|
|
- FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE
|
|
- | FEC_FECTFSR_TXW
|
|
- | FEC_FECTFSR_UF
|
|
- | FEC_FECTFSR_OF;
|
|
+ /* receive/transmit FIFO error */
|
|
+ if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0)) {
|
|
+ /* kill DMA receive channel */
|
|
+ MCD_killDma (fp->fecpriv_fec_rx_channel);
|
|
|
|
- // reset RFERR and XFERR event
|
|
- FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
|
|
+ /* kill running transmission by DMA */
|
|
+ MCD_killDma (fp->fecpriv_fec_tx_channel);
|
|
|
|
- // stop queue
|
|
- netif_stop_queue(dev);
|
|
-
|
|
- // execute reinitialization as tasklet
|
|
- tasklet_schedule(&fp->fecpriv_tasklet_reinit);
|
|
+ /* Reset FIFOs */
|
|
+ FEC_FECFRST(base_addr) |= FEC_SW_RST;
|
|
+ FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
|
|
|
|
- fp->fecpriv_stat.rx_dropped++;
|
|
+ /* reset receive FIFO status register */
|
|
+ FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE |
|
|
+ FEC_FECRFSR_RXW |
|
|
+ FEC_FECRFSR_UF;
|
|
|
|
- }
|
|
+ /* reset transmit FIFO status register */
|
|
+ FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE |
|
|
+ FEC_FECTFSR_TXW |
|
|
+ FEC_FECTFSR_UF |
|
|
+ FEC_FECTFSR_OF;
|
|
|
|
- // transmit FIFO underrun
|
|
- if ((events & FEC_EIR_XFUN) != 0)
|
|
- {
|
|
- // reset XFUN event
|
|
- FEC_EIR(base_addr) = FEC_EIR_XFUN;
|
|
- fp->fecpriv_stat.tx_aborted_errors++;
|
|
- }
|
|
+ /* reset RFERR and XFERR event */
|
|
+ FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
|
|
+
|
|
+ /* stop queue */
|
|
+ netif_stop_queue(dev);
|
|
+
|
|
+ /* execute reinitialization as tasklet */
|
|
+ tasklet_schedule(&fp->fecpriv_tasklet_reinit);
|
|
+
|
|
+ fp->fecpriv_stat.rx_dropped++;
|
|
+ }
|
|
|
|
- // late collision
|
|
- if ((events & FEC_EIR_LC) != 0)
|
|
- {
|
|
- // reset LC event
|
|
- FEC_EIR(base_addr) = FEC_EIR_LC;
|
|
+ /* transmit FIFO underrun */
|
|
+ if ((events & FEC_EIR_XFUN) != 0) {
|
|
+ /* reset XFUN event */
|
|
+ FEC_EIR(base_addr) = FEC_EIR_XFUN;
|
|
fp->fecpriv_stat.tx_aborted_errors++;
|
|
- }
|
|
+ }
|
|
|
|
- // collision retry limit
|
|
- if ((events & FEC_EIR_RL) != 0)
|
|
- {
|
|
- // reset RL event
|
|
- FEC_EIR(base_addr) = FEC_EIR_RL;
|
|
+ /* late collision */
|
|
+ if ((events & FEC_EIR_LC) != 0) {
|
|
+ /* reset LC event */
|
|
+ FEC_EIR(base_addr) = FEC_EIR_LC;
|
|
fp->fecpriv_stat.tx_aborted_errors++;
|
|
- }
|
|
+ }
|
|
|
|
- return 0;
|
|
+ /* collision retry limit */
|
|
+ if ((events & FEC_EIR_RL) != 0) {
|
|
+ /* reset RL event */
|
|
+ FEC_EIR(base_addr) = FEC_EIR_RL;
|
|
+ fp->fecpriv_stat.tx_aborted_errors++;
|
|
+ }
|
|
+ return 0;
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -1166,52 +1105,46 @@ void fec_interrupt_fec_reinit(unsigned l
|
|
struct fec_priv *fp = netdev_priv(dev);
|
|
unsigned long base_addr = (unsigned long) dev->base_addr;
|
|
|
|
- // Initialize reception descriptors and start DMA for the reception
|
|
- for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
|
|
- {
|
|
- if (!fp->askb_rx[i])
|
|
- {
|
|
- fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
|
|
- if (!fp->askb_rx[i])
|
|
- {
|
|
- fp->fecpriv_rxdesc[i].dataPointer = 0;
|
|
- fp->fecpriv_rxdesc[i].statCtrl = 0;
|
|
- fp->fecpriv_rxdesc[i].length = 0;
|
|
- continue;
|
|
- }
|
|
+ /* Initialize reception descriptors and start DMA for the reception */
|
|
+ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
|
|
+ if (!fp->askb_rx[i]) {
|
|
+ fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
|
|
+ if (!fp->askb_rx[i]) {
|
|
+ fp->fecpriv_rxdesc[i].dataPointer = 0;
|
|
+ fp->fecpriv_rxdesc[i].statCtrl = 0;
|
|
+ fp->fecpriv_rxdesc[i].length = 0;
|
|
+ continue;
|
|
+ }
|
|
fp->askb_rx[i]->dev = dev;
|
|
- skb_reserve(fp->askb_rx[i], 16);
|
|
- }
|
|
- fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
|
|
+ skb_reserve(fp->askb_rx[i], 16);
|
|
+ }
|
|
+ fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
|
|
fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
|
|
- fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
|
|
+ fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
|
|
}
|
|
|
|
fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
|
|
fp->fecpriv_current_rx = 0;
|
|
|
|
- // restart frame transmission
|
|
- for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
|
|
- {
|
|
- if (fp->fecpriv_txbuf[i])
|
|
- {
|
|
-
|
|
+ /* restart frame transmission */
|
|
+ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
|
|
+ if (fp->fecpriv_txbuf[i]) {
|
|
kfree(fp->fecpriv_txbuf[i]);
|
|
fp->fecpriv_txbuf[i] = NULL;
|
|
- fp->fecpriv_stat.tx_dropped++;
|
|
+ fp->fecpriv_stat.tx_dropped++;
|
|
}
|
|
fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
|
|
}
|
|
fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
|
|
fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
|
|
|
|
- // flush entire data cache before restarting the DMA
|
|
+ /* flush entire data cache before restarting the DMA */
|
|
#if 0
|
|
/* JKM -- currently running with cache turned off */
|
|
DcacheFlushInvalidate();
|
|
#endif
|
|
|
|
- // restart DMA from beginning
|
|
+ /* restart DMA from beginning */
|
|
MCD_startDma(fp->fecpriv_fec_rx_channel,
|
|
(char *) fp->fecpriv_rxdesc, 0,
|
|
(unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
|
|
@@ -1225,11 +1158,10 @@ void fec_interrupt_fec_reinit(unsigned l
|
|
FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
|
|
MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
|
|
|
|
- // Enable FEC
|
|
- FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
|
|
+ /* Enable FEC */
|
|
+ FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
|
|
|
|
netif_wake_queue(dev);
|
|
-
|
|
}
|
|
|
|
/************************************************************************
|
|
@@ -1284,8 +1216,8 @@ void fec_interrupt_fec_rx_handler_fec1(v
|
|
}
|
|
|
|
#endif
|
|
-#ifndef MODULE
|
|
|
|
+#ifndef MODULE
|
|
/************************************************************************
|
|
* NAME: fec_mac_setup0
|
|
*
|
|
@@ -1300,7 +1232,6 @@ int __init fec_mac_setup0(char *s)
|
|
if(fec_str_to_mac(s, fec_mac_addr_fec0))
|
|
printk("The MAC address of FEC0 cannot be set from command line");
|
|
return 1;
|
|
-
|
|
}
|
|
|
|
#ifdef FEC_2
|
|
@@ -1316,11 +1247,9 @@ int __init fec_mac_setup1(char *s)
|
|
if(!s || !*s)
|
|
return 1;
|
|
|
|
-
|
|
if(fec_str_to_mac(s, fec_mac_addr_fec1))
|
|
printk("The MAC address of FEC1 cannot be set from command line");
|
|
return 1;
|
|
-
|
|
}
|
|
#endif
|
|
|
|
@@ -1332,52 +1261,46 @@ int __init fec_mac_setup1(char *s)
|
|
*************************************************************************/
|
|
int fec_str_to_mac( char *str_mac, unsigned char* addr)
|
|
{
|
|
- unsigned long val;
|
|
+ unsigned long val;
|
|
char c;
|
|
unsigned long octet[6], *octetptr = octet;
|
|
int i;
|
|
-again:
|
|
|
|
+again:
|
|
val = 0;
|
|
- while ((c = *str_mac) != '\0')
|
|
- {
|
|
- if ((c>='0')&&(c<='9'))
|
|
- {
|
|
+ while ((c = *str_mac) != '\0') {
|
|
+ if ((c>='0')&&(c<='9')) {
|
|
val = (val * 16) + (c - '0');
|
|
str_mac++;
|
|
continue;
|
|
}
|
|
- else
|
|
- if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F')))
|
|
- {
|
|
+ else if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F'))) {
|
|
val = (val << 4) + (c + 10 - (((c>='a')&&(c<='f')) ? 'a' : 'A'));
|
|
str_mac++;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
- if (*str_mac == ':')
|
|
- {
|
|
+ if (*str_mac == ':') {
|
|
*octetptr++ = val, str_mac++;
|
|
if (octetptr >= octet + 6)
|
|
return 1;
|
|
goto again;
|
|
}
|
|
|
|
- //Check for trailing characters.
|
|
+ /* Check for trailing characters */
|
|
if (*str_mac && !(*str_mac==' '))
|
|
return 1;
|
|
+
|
|
*octetptr++ = val;
|
|
|
|
- if ((octetptr - octet)==6)
|
|
- {
|
|
- for(i=0;i<=6;i++)
|
|
- addr[i]=octet[i];
|
|
+ if ((octetptr - octet)==6) {
|
|
+ for(i=0;i<=6;i++)
|
|
+ addr[i]=octet[i];
|
|
}
|
|
- else
|
|
+ else
|
|
return 1;
|
|
|
|
return 0;
|
|
-
|
|
}
|
|
#endif
|