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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
44 lines
1.3 KiB
Diff
44 lines
1.3 KiB
Diff
From 156560a512a39284148d556ab96e2e833e816666 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 23 Dec 2011 19:25:42 +0100
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Subject: [PATCH 27/27] watchdog: ath79_wdt: flush register writes
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The watchdog register writes required to have a flush
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in order to commit the values to the register. Without
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the flush, the driver not function correctly on AR934X
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SoCs.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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---
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drivers/watchdog/ath79_wdt.c | 6 ++++++
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1 files changed, 6 insertions(+), 0 deletions(-)
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--- a/drivers/watchdog/ath79_wdt.c
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+++ b/drivers/watchdog/ath79_wdt.c
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@@ -68,17 +68,23 @@ static int max_timeout;
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static inline void ath79_wdt_keepalive(void)
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{
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ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
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+ /* flush write */
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+ ath79_reset_rr(AR71XX_RESET_REG_WDOG);
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}
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static inline void ath79_wdt_enable(void)
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{
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ath79_wdt_keepalive();
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
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+ /* flush write */
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+ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
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}
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static inline void ath79_wdt_disable(void)
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{
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ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
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+ /* flush write */
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+ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
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}
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static int ath79_wdt_set_timeout(int val)
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