mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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12a0868f92
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24087 3c298f89-4303-0410-b956-a3cf2f4a3e73
205 lines
6.9 KiB
C
205 lines
6.9 KiB
C
/*
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* Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved.
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* Author: Chenghu Wu <b16972@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __MCFFEC_H__
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#define __MCFFEC_H
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/platform_device.h>
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#include <asm/pgtable.h>
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/* The FEC stores dest/src/type, data, and checksum for receive packets.
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*/
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#define PKT_MAXBUF_SIZE 1518
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/*
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* The 5270/5271/5280/5282/532x RX control register also contains maximum frame
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* size bits. Other FEC hardware does not, so we need to take that into
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* account when setting it.
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*/
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
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defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \
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defined(CONFIG_M5445X)
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#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
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#else
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#define OPT_FRAME_SIZE 0
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#endif
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/*
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* Some hardware gets it MAC address out of local flash memory.
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* if this is non-zero then assume it is the address to get MAC from.
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*/
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#if defined(CONFIG_NETtel)
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#define FEC_FLASHMAC 0xf0006006
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#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
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#define FEC_FLASHMAC 0xf0006000
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#elif defined(CONFIG_CANCam)
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#define FEC_FLASHMAC 0xf0020000
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#elif defined(CONFIG_M5272C3)
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#define FEC_FLASHMAC (0xffe04000 + 4)
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#elif defined(CONFIG_MOD5272)
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#define FEC_FLASHMAC 0xffc0406b
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#else
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#define FEC_FLASHMAC 0
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#endif
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#ifdef CONFIG_FEC_DMA_USE_SRAM
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#define TX_RING_SIZE 8 /* Must be power of two */
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#define TX_RING_MOD_MASK 7 /* for this to work */
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#else
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#define TX_RING_SIZE 16 /* Must be power of two */
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#define TX_RING_MOD_MASK 15 /* for this to work */
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#endif
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typedef struct fec {
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unsigned long fec_reserved0;
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unsigned long fec_ievent; /* Interrupt event reg */
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unsigned long fec_imask; /* Interrupt mask reg */
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unsigned long fec_reserved1;
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unsigned long fec_r_des_active; /* Receive descriptor reg */
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unsigned long fec_x_des_active; /* Transmit descriptor reg */
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unsigned long fec_reserved2[3];
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unsigned long fec_ecntrl; /* Ethernet control reg */
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unsigned long fec_reserved3[6];
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unsigned long fec_mii_data; /* MII manage frame reg */
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unsigned long fec_mii_speed; /* MII speed control reg */
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unsigned long fec_reserved4[7];
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unsigned long fec_mib_ctrlstat; /* MIB control/status reg */
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unsigned long fec_reserved5[7];
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unsigned long fec_r_cntrl; /* Receive control reg */
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unsigned long fec_reserved6[15];
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unsigned long fec_x_cntrl; /* Transmit Control reg */
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unsigned long fec_reserved7[7];
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unsigned long fec_addr_low; /* Low 32bits MAC address */
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unsigned long fec_addr_high; /* High 16bits MAC address */
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unsigned long fec_opd; /* Opcode + Pause duration */
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unsigned long fec_reserved8[10];
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unsigned long fec_hash_table_high; /* High 32bits hash table */
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unsigned long fec_hash_table_low; /* Low 32bits hash table */
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unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
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unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
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unsigned long fec_reserved9[7];
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unsigned long fec_x_wmrk; /* FIFO transmit water mark */
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unsigned long fec_reserved10;
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unsigned long fec_r_bound; /* FIFO receive bound reg */
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unsigned long fec_r_fstart; /* FIFO receive start reg */
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unsigned long fec_reserved11[11];
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unsigned long fec_r_des_start; /* Receive descriptor ring */
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unsigned long fec_x_des_start; /* Transmit descriptor ring */
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unsigned long fec_r_buff_size; /* Maximum receive buff size */
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} fec_t;
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/*
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* Define the buffer descriptor structure.
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*/
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typedef struct bufdesc {
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unsigned short cbd_sc; /* Control and status info */
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unsigned short cbd_datlen; /* Data length */
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unsigned long cbd_bufaddr; /* Buffer address */
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} cbd_t;
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/* Forward declarations of some structures to support different PHYs
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*/
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typedef struct {
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uint mii_data;
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void (*funct)(uint mii_reg, struct net_device *dev);
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} phy_cmd_t;
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typedef struct {
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uint id;
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char *name;
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const phy_cmd_t *config;
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const phy_cmd_t *startup;
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const phy_cmd_t *ack_int;
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const phy_cmd_t *shutdown;
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} phy_info_t;
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/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
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* tx_bd_base always point to the base of the buffer descriptors. The
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* cur_rx and cur_tx point to the currently available buffer.
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* The dirty_tx tracks the current buffer that is being sent by the
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* controller. The cur_tx and dirty_tx are equal under both completely
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* empty and completely full conditions. The empty/ready indicator in
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* the buffer descriptor determines the actual condition.
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*/
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struct fec_enet_private {
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/* Hardware registers of the FEC device */
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volatile fec_t *hwp;
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struct net_device *netdev;
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struct platform_device *pdev;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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ushort skb_cur;
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ushort skb_dirty;
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/* CPM dual port RAM relative addresses.
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*/
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cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
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cbd_t *tx_bd_base;
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cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
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cbd_t *dirty_tx; /* The ring entries to be free()ed. */
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uint tx_full;
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/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
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spinlock_t hw_lock;
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/* hold while accessing the mii_list_t() elements */
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spinlock_t mii_lock;
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struct mii_bus *mdio_bus;
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struct phy_device *phydev;
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uint phy_id;
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uint phy_id_done;
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uint phy_status;
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uint phy_speed;
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phy_info_t const *phy;
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struct work_struct phy_task;
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volatile fec_t *phy_hwp;
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uint sequence_done;
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uint mii_phy_task_queued;
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uint phy_addr;
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int index;
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int opened;
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int link;
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int old_link;
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int full_duplex;
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int duplex;
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int speed;
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int msg_enable;
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};
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struct fec_platform_private {
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struct platform_device *pdev;
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unsigned long quirks;
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int num_slots; /* Slots on controller */
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struct fec_enet_private *fep_host[0]; /* Pointers to hosts */
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};
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#endif
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