mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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c7f17e256a
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23132 3c298f89-4303-0410-b956-a3cf2f4a3e73
607 lines
13 KiB
C
607 lines
13 KiB
C
/*
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* Atheros AR71xx SoC platform devices
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include "devices.h"
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unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
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static struct resource ar71xx_uart_resources[] = {
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{
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.start = AR71XX_UART_BASE,
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.end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
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static struct plat_serial8250_port ar71xx_uart_data[] = {
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{
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.mapbase = AR71XX_UART_BASE,
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.irq = AR71XX_MISC_IRQ_UART,
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.flags = AR71XX_UART_FLAGS,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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}, {
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/* terminating entry */
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}
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};
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static struct platform_device ar71xx_uart_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.resource = ar71xx_uart_resources,
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.num_resources = ARRAY_SIZE(ar71xx_uart_resources),
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.dev = {
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.platform_data = ar71xx_uart_data
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},
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};
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void __init ar71xx_add_device_uart(void)
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{
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ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
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platform_device_register(&ar71xx_uart_device);
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}
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static struct resource ar71xx_mdio_resources[] = {
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{
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.name = "mdio_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE0_BASE,
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.end = AR71XX_GE0_BASE + 0x200 - 1,
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}
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};
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static struct ag71xx_mdio_platform_data ar71xx_mdio_data;
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struct platform_device ar71xx_mdio_device = {
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.name = "ag71xx-mdio",
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.id = -1,
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.resource = ar71xx_mdio_resources,
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.num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
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.dev = {
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.platform_data = &ar71xx_mdio_data,
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},
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};
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void __init ar71xx_add_device_mdio(u32 phy_mask)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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ar71xx_mdio_data.is_ar7240 = 1;
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break;
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case AR71XX_SOC_AR7241:
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ar71xx_mdio_data.is_ar7240 = 1;
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ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
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ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
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break;
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case AR71XX_SOC_AR7242:
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ar71xx_mdio_data.is_ar7240 = 1;
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break;
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default:
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break;
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}
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ar71xx_mdio_data.phy_mask = phy_mask;
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platform_device_register(&ar71xx_mdio_device);
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}
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static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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{
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void __iomem *base;
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u32 t;
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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t = __raw_readl(base + cfg_reg);
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t &= ~(3 << shift);
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t |= (2 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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__raw_writel(pll_val, base + pll_reg);
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t |= (3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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t &= ~(3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
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(unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
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iounmap(base);
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}
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struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
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struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
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static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
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{
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struct ar71xx_eth_pll_data *pll_data;
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u32 pll_val;
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switch (mac) {
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case 0:
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pll_data = &ar71xx_eth0_pll_data;
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break;
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case 1:
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pll_data = &ar71xx_eth1_pll_data;
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break;
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default:
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BUG();
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}
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switch (speed) {
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case SPEED_10:
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pll_val = pll_data->pll_10;
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break;
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case SPEED_100:
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pll_val = pll_data->pll_100;
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break;
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case SPEED_1000:
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pll_val = pll_data->pll_1000;
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break;
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default:
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BUG();
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}
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return pll_val;
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}
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static void ar71xx_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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}
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static void ar71xx_set_pll_ge1(int speed)
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{
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u32 val = ar71xx_get_eth_pll(1, speed);
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR71XX_ETH1_PLL_SHIFT);
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}
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static void ar724x_set_pll_ge0(int speed)
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{
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/* TODO */
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}
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static void ar724x_set_pll_ge1(int speed)
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{
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/* TODO */
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}
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static void ar91xx_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR91XX_ETH0_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge1(int speed)
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{
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u32 val = ar71xx_get_eth_pll(1, speed);
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR91XX_ETH1_PLL_SHIFT);
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}
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static void ar71xx_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
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}
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static void ar71xx_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
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}
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static void ar724x_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
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}
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static void ar724x_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
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}
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static void ar91xx_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
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}
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static void ar91xx_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
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}
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static struct resource ar71xx_eth0_resources[] = {
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{
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.name = "mac_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE0_BASE,
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.end = AR71XX_GE0_BASE + 0x200 - 1,
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}, {
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.name = "mii_ctrl",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
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.end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
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}, {
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.name = "mac_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR71XX_CPU_IRQ_GE0,
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.end = AR71XX_CPU_IRQ_GE0,
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},
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};
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struct ag71xx_platform_data ar71xx_eth0_data = {
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.reset_bit = RESET_MODULE_GE0_MAC,
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};
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struct platform_device ar71xx_eth0_device = {
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.name = "ag71xx",
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.id = 0,
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.resource = ar71xx_eth0_resources,
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.num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
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.dev = {
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.platform_data = &ar71xx_eth0_data,
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},
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};
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static struct resource ar71xx_eth1_resources[] = {
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{
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.name = "mac_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE1_BASE,
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.end = AR71XX_GE1_BASE + 0x200 - 1,
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}, {
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.name = "mii_ctrl",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
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.end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
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}, {
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.name = "mac_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR71XX_CPU_IRQ_GE1,
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.end = AR71XX_CPU_IRQ_GE1,
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},
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};
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struct ag71xx_platform_data ar71xx_eth1_data = {
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.reset_bit = RESET_MODULE_GE1_MAC,
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};
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struct platform_device ar71xx_eth1_device = {
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.name = "ag71xx",
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.id = 1,
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.resource = ar71xx_eth1_resources,
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.num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
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.dev = {
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.platform_data = &ar71xx_eth1_data,
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},
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};
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#define AR71XX_PLL_VAL_1000 0x00110000
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#define AR71XX_PLL_VAL_100 0x00001099
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#define AR71XX_PLL_VAL_10 0x00991099
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#define AR724X_PLL_VAL_1000 0x00110000
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#define AR724X_PLL_VAL_100 0x00001099
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#define AR724X_PLL_VAL_10 0x00991099
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#define AR91XX_PLL_VAL_1000 0x1a000000
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#define AR91XX_PLL_VAL_100 0x13000a44
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#define AR91XX_PLL_VAL_10 0x00441099
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static void __init ar71xx_init_eth_pll_data(unsigned int id)
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{
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struct ar71xx_eth_pll_data *pll_data;
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u32 pll_10, pll_100, pll_1000;
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switch (id) {
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case 0:
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pll_data = &ar71xx_eth0_pll_data;
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break;
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case 1:
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pll_data = &ar71xx_eth1_pll_data;
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break;
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default:
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BUG();
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}
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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pll_10 = AR71XX_PLL_VAL_10;
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pll_100 = AR71XX_PLL_VAL_100;
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pll_1000 = AR71XX_PLL_VAL_1000;
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break;
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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pll_10 = AR724X_PLL_VAL_10;
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pll_100 = AR724X_PLL_VAL_100;
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pll_1000 = AR724X_PLL_VAL_1000;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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pll_10 = AR91XX_PLL_VAL_10;
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pll_100 = AR91XX_PLL_VAL_100;
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pll_1000 = AR91XX_PLL_VAL_1000;
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break;
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default:
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BUG();
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}
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if (!pll_data->pll_10)
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pll_data->pll_10 = pll_10;
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if (!pll_data->pll_100)
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pll_data->pll_100 = pll_100;
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if (!pll_data->pll_1000)
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pll_data->pll_1000 = pll_1000;
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}
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static int ar71xx_eth_instance __initdata;
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void __init ar71xx_add_device_eth(unsigned int id)
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{
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struct platform_device *pdev;
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struct ag71xx_platform_data *pdata;
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ar71xx_init_eth_pll_data(id);
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switch (id) {
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case 0:
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switch (ar71xx_eth0_data.phy_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
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break;
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case PHY_INTERFACE_MODE_GMII:
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ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
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break;
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default:
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printk(KERN_ERR "ar71xx: invalid PHY interface mode "
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"for eth0\n");
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return;
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}
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pdev = &ar71xx_eth0_device;
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break;
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case 1:
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switch (ar71xx_eth1_data.phy_if_mode) {
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case PHY_INTERFACE_MODE_RMII:
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ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
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break;
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default:
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printk(KERN_ERR "ar71xx: invalid PHY interface mode "
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"for eth1\n");
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return;
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}
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pdev = &ar71xx_eth1_device;
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break;
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default:
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printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
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return;
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}
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pdata = pdev->dev.platform_data;
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
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: ar71xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar71xx_set_pll_ge1
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: ar71xx_set_pll_ge0;
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break;
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
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: ar71xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar71xx_set_pll_ge1
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: ar71xx_set_pll_ge0;
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pdata->has_gbit = 1;
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break;
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
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ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
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/* fall through */
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case AR71XX_SOC_AR7240:
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pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
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: ar724x_ddr_flush_ge0;
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pdata->set_pll = id ? ar724x_set_pll_ge1
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: ar724x_set_pll_ge0;
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pdata->is_ar724x = 1;
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if (!pdata->fifo_cfg1)
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pdata->fifo_cfg1 = 0x0010ffff;
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if (!pdata->fifo_cfg2)
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pdata->fifo_cfg2 = 0x015500aa;
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if (!pdata->fifo_cfg3)
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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case AR71XX_SOC_AR9130:
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pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
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: ar91xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar91xx_set_pll_ge1
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: ar91xx_set_pll_ge0;
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pdata->is_ar91xx = 1;
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break;
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case AR71XX_SOC_AR9132:
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pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
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: ar91xx_ddr_flush_ge0;
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pdata->set_pll = id ? ar91xx_set_pll_ge1
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: ar91xx_set_pll_ge0;
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pdata->is_ar91xx = 1;
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pdata->has_gbit = 1;
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break;
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default:
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BUG();
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}
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switch (pdata->phy_if_mode) {
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case PHY_INTERFACE_MODE_GMII:
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case PHY_INTERFACE_MODE_RGMII:
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if (!pdata->has_gbit) {
|
|
printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
|
|
id);
|
|
return;
|
|
}
|
|
/* fallthrough */
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!is_valid_ether_addr(pdata->mac_addr)) {
|
|
random_ether_addr(pdata->mac_addr);
|
|
printk(KERN_DEBUG
|
|
"ar71xx: using random MAC address for eth%d\n",
|
|
ar71xx_eth_instance);
|
|
}
|
|
|
|
if (pdata->mii_bus_dev == NULL)
|
|
pdata->mii_bus_dev = &ar71xx_mdio_device.dev;
|
|
|
|
/* Reset the device */
|
|
ar71xx_device_stop(pdata->reset_bit);
|
|
mdelay(100);
|
|
|
|
ar71xx_device_start(pdata->reset_bit);
|
|
mdelay(100);
|
|
|
|
platform_device_register(pdev);
|
|
ar71xx_eth_instance++;
|
|
}
|
|
|
|
static struct resource ar71xx_spi_resources[] = {
|
|
[0] = {
|
|
.start = AR71XX_SPI_BASE,
|
|
.end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device ar71xx_spi_device = {
|
|
.name = "ar71xx-spi",
|
|
.id = -1,
|
|
.resource = ar71xx_spi_resources,
|
|
.num_resources = ARRAY_SIZE(ar71xx_spi_resources),
|
|
};
|
|
|
|
void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
|
|
struct spi_board_info const *info,
|
|
unsigned n)
|
|
{
|
|
spi_register_board_info(info, n);
|
|
ar71xx_spi_device.dev.platform_data = pdata;
|
|
platform_device_register(&ar71xx_spi_device);
|
|
}
|
|
|
|
void __init ar71xx_add_device_wdt(void)
|
|
{
|
|
platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
|
|
}
|
|
|
|
void __init ar71xx_set_mac_base(unsigned char *mac)
|
|
{
|
|
memcpy(ar71xx_mac_base, mac, ETH_ALEN);
|
|
}
|
|
|
|
void __init ar71xx_parse_mac_addr(char *mac_str)
|
|
{
|
|
u8 tmp[ETH_ALEN];
|
|
int t;
|
|
|
|
t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
|
|
&tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
|
|
|
|
if (t != ETH_ALEN)
|
|
t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
|
|
&tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
|
|
|
|
if (t == ETH_ALEN)
|
|
ar71xx_set_mac_base(tmp);
|
|
else
|
|
printk(KERN_DEBUG "ar71xx: failed to parse mac address "
|
|
"\"%s\"\n", mac_str);
|
|
}
|
|
|
|
static int __init ar71xx_ethaddr_setup(char *str)
|
|
{
|
|
ar71xx_parse_mac_addr(str);
|
|
return 1;
|
|
}
|
|
__setup("ethaddr=", ar71xx_ethaddr_setup);
|
|
|
|
static int __init ar71xx_kmac_setup(char *str)
|
|
{
|
|
ar71xx_parse_mac_addr(str);
|
|
return 1;
|
|
}
|
|
__setup("kmac=", ar71xx_kmac_setup);
|
|
|
|
void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
|
|
unsigned offset)
|
|
{
|
|
u32 t;
|
|
|
|
if (!is_valid_ether_addr(src)) {
|
|
memset(dst, '\0', ETH_ALEN);
|
|
return;
|
|
}
|
|
|
|
t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
|
|
t += offset;
|
|
|
|
dst[0] = src[0];
|
|
dst[1] = src[1];
|
|
dst[2] = src[2];
|
|
dst[3] = (t >> 16) & 0xff;
|
|
dst[4] = (t >> 8) & 0xff;
|
|
dst[5] = t & 0xff;
|
|
}
|