mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-21 09:49:54 +02:00
4f531230a3
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
712 lines
16 KiB
C
712 lines
16 KiB
C
/*
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* Misc useful routines to access NIC SROM
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id$
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*/
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#include <typedefs.h>
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#include <osl.h>
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#include <bcmutils.h>
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#include <bcmsrom.h>
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#include <bcmdevs.h>
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#include <bcmendian.h>
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#include <sbpcmcia.h>
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#include <pcicfg.h>
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#include <sbutils.h>
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#include <proto/ethernet.h> /* for sprom content groking */
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#define VARS_MAX 4096 /* should be reduced */
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static int initvars_srom_pci(void *curmap, char **vars, int *count);
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static int initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count);
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static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
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static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
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static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
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static int sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc);
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/*
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* Initialize the vars from the right source for this platform.
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* Return 0 on success, nonzero on error.
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*/
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int
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srom_var_init(void *sbh, uint bus, void *curmap, void *osh, char **vars, int *count)
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{
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if (vars == NULL)
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return (0);
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switch (bus) {
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case SB_BUS:
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/* These two could be asserts ... */
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*vars = NULL;
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*count = 0;
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return(0);
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case PCI_BUS:
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ASSERT(curmap); /* can not be NULL */
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return(initvars_srom_pci(curmap, vars, count));
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case PCMCIA_BUS:
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return(initvars_cis_pcmcia(sbh, curmap, osh, vars, count));
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default:
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ASSERT(0);
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}
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return (-1);
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}
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/* support only 16-bit word read from srom */
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int
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srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
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{
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void *srom;
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uint i, off, nw;
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/* check input - 16-bit access only */
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if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
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return 1;
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if (bus == PCI_BUS) {
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if (!curmap)
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return 1;
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srom = (void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
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if (sprom_read_pci(srom, byteoff, buf, nbytes, FALSE))
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return 1;
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} else if (bus == PCMCIA_BUS) {
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off = byteoff / 2;
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nw = nbytes / 2;
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for (i = 0; i < nw; i++) {
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if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
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return 1;
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}
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} else {
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return 1;
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}
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return 0;
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}
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/* support only 16-bit word write into srom */
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int
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srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
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{
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uint16 *srom;
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uint i, off, nw, crc_range;
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uint16 image[SPROM_SIZE], *p;
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uint8 crc;
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volatile uint32 val32;
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/* check input - 16-bit access only */
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if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
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return 1;
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crc_range = ((bus == PCMCIA_BUS) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
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/* if changes made inside crc cover range */
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if (byteoff < crc_range) {
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nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
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/* read data including entire first 64 words from srom */
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if (srom_read(bus, curmap, osh, 0, nw * 2, image))
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return 1;
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/* make changes */
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bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
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/* calculate crc */
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htol16_buf(image, crc_range);
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crc = ~crc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
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ltoh16_buf(image, crc_range);
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image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
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p = image;
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off = 0;
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} else {
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p = buf;
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off = byteoff / 2;
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nw = nbytes / 2;
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}
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if (bus == PCI_BUS) {
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srom = (uint16*)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
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/* enable writes to the SPROM */
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val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
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val32 |= SPROM_WRITEEN;
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OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
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bcm_mdelay(500);
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/* write srom */
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for (i = 0; i < nw; i++) {
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W_REG(&srom[off + i], p[i]);
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bcm_mdelay(20);
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}
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/* disable writes to the SPROM */
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OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
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} else if (bus == PCMCIA_BUS) {
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/* enable writes to the SPROM */
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if (sprom_cmd_pcmcia(osh, SROM_WEN))
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return 1;
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bcm_mdelay(500);
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/* write srom */
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for (i = 0; i < nw; i++) {
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sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
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bcm_mdelay(20);
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}
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/* disable writes to the SPROM */
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if (sprom_cmd_pcmcia(osh, SROM_WDS))
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return 1;
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} else {
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return 1;
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}
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bcm_mdelay(500);
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return 0;
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}
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int
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srom_parsecis(uint8 *cis, char **vars, int *count)
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{
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char eabuf[32];
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char *vp, *base;
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uint8 tup, tlen, sromrev = 1;
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int i, j;
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uint varsize;
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bool ag_init = FALSE;
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uint16 w;
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ASSERT(vars);
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ASSERT(count);
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base = vp = MALLOC(VARS_MAX);
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ASSERT(vp);
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i = 0;
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do {
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tup = cis[i++];
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tlen = cis[i++];
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if ((i + tlen) >= CIS_SIZE)
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break;
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switch (tup) {
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case CISTPL_MANFID:
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vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
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vp++;
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vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
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vp++;
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break;
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case CISTPL_FUNCE:
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if (cis[i] == LAN_NID) {
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ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
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bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
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vp += sprintf(vp, "il0macaddr=%s", eabuf);
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vp++;
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}
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break;
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case CISTPL_CFTABLE:
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vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
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vp++;
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break;
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case CISTPL_BRCM_HNBU:
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switch (cis[i]) {
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case HNBU_CHIPID:
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vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
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vp++;
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vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
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vp++;
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if (tlen == 7) {
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vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
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vp++;
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}
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break;
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case HNBU_BOARDREV:
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vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
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vp++;
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break;
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case HNBU_AA:
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vp += sprintf(vp, "aa0=%d", cis[i + 1]);
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vp++;
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break;
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case HNBU_AG:
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vp += sprintf(vp, "ag0=%d", cis[i + 1]);
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vp++;
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ag_init = TRUE;
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break;
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case HNBU_CC:
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vp += sprintf(vp, "cc=%d", cis[i + 1]);
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vp++;
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break;
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case HNBU_PAPARMS:
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vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
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vp++;
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if (tlen == 9) {
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/* New version */
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for (j = 0; j < 3; j++) {
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vp += sprintf(vp, "pa0b%d=%d", j,
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(cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
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vp++;
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}
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vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
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vp++;
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}
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break;
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case HNBU_OEM:
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vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
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cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
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cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
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vp++;
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break;
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case HNBU_BOARDFLAGS:
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w = (cis[i + 2] << 8) + cis[i + 1];
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if (w == 0xffff) w = 0;
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vp += sprintf(vp, "boardflags=%d", w);
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vp++;
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break;
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case HNBU_LED:
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if (cis[i + 1] != 0xff) {
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vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
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vp++;
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}
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if (cis[i + 2] != 0xff) {
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vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
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vp++;
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}
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if (cis[i + 3] != 0xff) {
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vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
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vp++;
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}
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if (cis[i + 4] != 0xff) {
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vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
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vp++;
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}
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break;
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}
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break;
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}
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i += tlen;
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} while (tup != 0xff);
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/* Set the srom version */
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vp += sprintf(vp, "sromrev=%d", sromrev);
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vp++;
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/* For now just set boardflags2 to zero */
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vp += sprintf(vp, "boardflags2=0");
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vp++;
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/* if there is no antenna gain field, set default */
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if (ag_init == FALSE) {
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vp += sprintf(vp, "ag0=%d", 0xff);
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vp++;
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}
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/* final nullbyte terminator */
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*vp++ = '\0';
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varsize = (uint)vp - (uint)base;
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ASSERT(varsize < VARS_MAX);
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if (varsize == VARS_MAX) {
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*vars = base;
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} else {
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vp = MALLOC(varsize);
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ASSERT(vp);
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bcopy(base, vp, varsize);
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MFREE(base, VARS_MAX);
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*vars = vp;
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}
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*count = varsize;
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return (0);
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}
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/* set PCMCIA sprom command register */
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static int
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sprom_cmd_pcmcia(void *osh, uint8 cmd)
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{
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uint8 status;
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uint wait_cnt = 1000;
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/* write sprom command register */
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
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/* wait status */
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while (wait_cnt--) {
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OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
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if (status & SROM_DONE)
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return 0;
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}
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return 1;
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}
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/* read a word from the PCMCIA srom */
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static int
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sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
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{
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uint8 addr_l, addr_h, data_l, data_h;
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addr_l = (uint8)((addr * 2) & 0xff);
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addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
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/* set address */
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
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/* do read */
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if (sprom_cmd_pcmcia(osh, SROM_READ))
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return 1;
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/* read data */
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OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
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OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
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*data = (data_h << 8) | data_l;
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return 0;
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}
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/* write a word to the PCMCIA srom */
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static int
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sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
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{
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uint8 addr_l, addr_h, data_l, data_h;
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addr_l = (uint8)((addr * 2) & 0xff);
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addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
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data_l = (uint8)(data & 0xff);
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data_h = (uint8)((data >> 8) & 0xff);
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/* set address */
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
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/* write data */
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
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OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
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/* do write */
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return sprom_cmd_pcmcia(osh, SROM_WRITE);
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}
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/*
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* Read in and validate sprom.
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* Return 0 on success, nonzero on error.
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*/
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static int
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sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc)
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{
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int off, nw;
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uint8 chk8;
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int i;
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off = byteoff / 2;
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nw = ROUNDUP(nbytes, 2) / 2;
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/* read the sprom */
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for (i = 0; i < nw; i++)
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buf[i] = R_REG(&sprom[off + i]);
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if (check_crc) {
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, nw * 2);
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if ((chk8 = crc8((uchar*)buf, nbytes, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
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return (1);
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, nw * 2);
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}
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return (0);
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}
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/*
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* Initialize nonvolatile variable table from sprom.
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* Return 0 on success, nonzero on error.
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*/
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static int
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initvars_srom_pci(void *curmap, char **vars, int *count)
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{
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uint16 w, b[64];
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uint8 sromrev;
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struct ether_addr ea;
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char eabuf[32];
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uint32 bfl;
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int c, woff, i;
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char *vp, *base;
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if (sprom_read_pci((void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof (b), TRUE))
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return (-1);
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/* top word of sprom contains version and crc8 */
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sromrev = b[63] & 0xff;
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if ((sromrev != 1) && (sromrev != 2)) {
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return (-2);
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}
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ASSERT(vars);
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ASSERT(count);
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base = vp = MALLOC(VARS_MAX);
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ASSERT(vp);
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vp += sprintf(vp, "sromrev=%d", sromrev);
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vp++;
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if (sromrev >= 2) {
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/* New section takes over the 4th hardware function space */
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/* Word 29 is max power 11a high/low */
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w = b[29];
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vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
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vp++;
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vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
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vp++;
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/* Words 30-32 set the 11alow pa settings,
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* 33-35 are the 11ahigh ones.
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*/
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for (i = 0; i < 3; i++) {
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vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
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vp++;
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vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
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vp++;
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}
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w = b[59];
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if (w == 0)
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vp += sprintf(vp, "ccode=");
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else
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vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
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vp++;
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}
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/* parameter section of sprom starts at byte offset 72 */
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woff = 72/2;
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/* first 6 bytes are il0macaddr */
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ea.octet[0] = (b[woff] >> 8) & 0xff;
|
|
ea.octet[1] = b[woff] & 0xff;
|
|
ea.octet[2] = (b[woff+1] >> 8) & 0xff;
|
|
ea.octet[3] = b[woff+1] & 0xff;
|
|
ea.octet[4] = (b[woff+2] >> 8) & 0xff;
|
|
ea.octet[5] = b[woff+2] & 0xff;
|
|
woff += ETHER_ADDR_LEN/2 ;
|
|
bcm_ether_ntoa((uchar*)&ea, eabuf);
|
|
vp += sprintf(vp, "il0macaddr=%s", eabuf);
|
|
vp++;
|
|
|
|
/* next 6 bytes are et0macaddr */
|
|
ea.octet[0] = (b[woff] >> 8) & 0xff;
|
|
ea.octet[1] = b[woff] & 0xff;
|
|
ea.octet[2] = (b[woff+1] >> 8) & 0xff;
|
|
ea.octet[3] = b[woff+1] & 0xff;
|
|
ea.octet[4] = (b[woff+2] >> 8) & 0xff;
|
|
ea.octet[5] = b[woff+2] & 0xff;
|
|
woff += ETHER_ADDR_LEN/2 ;
|
|
bcm_ether_ntoa((uchar*)&ea, eabuf);
|
|
vp += sprintf(vp, "et0macaddr=%s", eabuf);
|
|
vp++;
|
|
|
|
/* next 6 bytes are et1macaddr */
|
|
ea.octet[0] = (b[woff] >> 8) & 0xff;
|
|
ea.octet[1] = b[woff] & 0xff;
|
|
ea.octet[2] = (b[woff+1] >> 8) & 0xff;
|
|
ea.octet[3] = b[woff+1] & 0xff;
|
|
ea.octet[4] = (b[woff+2] >> 8) & 0xff;
|
|
ea.octet[5] = b[woff+2] & 0xff;
|
|
woff += ETHER_ADDR_LEN/2 ;
|
|
bcm_ether_ntoa((uchar*)&ea, eabuf);
|
|
vp += sprintf(vp, "et1macaddr=%s", eabuf);
|
|
vp++;
|
|
|
|
/*
|
|
* Enet phy settings one or two singles or a dual
|
|
* Bits 4-0 : MII address for enet0 (0x1f for not there)
|
|
* Bits 9-5 : MII address for enet1 (0x1f for not there)
|
|
* Bit 14 : Mdio for enet0
|
|
* Bit 15 : Mdio for enet1
|
|
*/
|
|
w = b[woff];
|
|
vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
|
|
vp++;
|
|
vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
|
|
vp++;
|
|
vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
|
|
vp++;
|
|
vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
|
|
vp++;
|
|
|
|
/* Word 46 has board rev, antennas 0/1 & Country code/control */
|
|
w = b[46];
|
|
vp += sprintf(vp, "boardrev=%d", w & 0xff);
|
|
vp++;
|
|
|
|
if (sromrev > 1)
|
|
vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
|
|
else
|
|
vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
|
|
vp++;
|
|
|
|
vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
|
|
vp++;
|
|
|
|
vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
|
|
vp++;
|
|
|
|
/* Words 47-49 set the (wl) pa settings */
|
|
woff = 47;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
|
|
vp++;
|
|
vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
|
|
vp++;
|
|
}
|
|
|
|
/*
|
|
* Words 50-51 set the customer-configured wl led behavior.
|
|
* 8 bits/gpio pin. High bit: activehi=0, activelo=1;
|
|
* LED behavior values defined in wlioctl.h .
|
|
*/
|
|
w = b[50];
|
|
if ((w != 0) && (w != 0xffff)) {
|
|
/* gpio0 */
|
|
vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
|
|
vp++;
|
|
|
|
/* gpio1 */
|
|
vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
|
|
vp++;
|
|
}
|
|
w = b[51];
|
|
if ((w != 0) && (w != 0xffff)) {
|
|
/* gpio2 */
|
|
vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
|
|
vp++;
|
|
|
|
/* gpio3 */
|
|
vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
|
|
vp++;
|
|
}
|
|
|
|
/* Word 52 is max power 0/1 */
|
|
w = b[52];
|
|
vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
|
|
vp++;
|
|
vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
|
|
vp++;
|
|
|
|
/* Word 56 is idle tssi target 0/1 */
|
|
w = b[56];
|
|
vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
|
|
vp++;
|
|
vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
|
|
vp++;
|
|
|
|
/* Word 57 is boardflags, if not programmed make it zero */
|
|
bfl = (uint32)b[57];
|
|
if (bfl == 0xffff) bfl = 0;
|
|
if (sromrev > 1) {
|
|
/* Word 28 is boardflags2 */
|
|
bfl |= (uint32)b[28] << 16;
|
|
}
|
|
vp += sprintf(vp, "boardflags=%d", bfl);
|
|
vp++;
|
|
|
|
/* Word 58 is antenna gain 0/1 */
|
|
w = b[58];
|
|
vp += sprintf(vp, "ag0=%d", w & 0xff);
|
|
vp++;
|
|
|
|
vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
|
|
vp++;
|
|
|
|
if (sromrev == 1) {
|
|
/* set the oem string */
|
|
vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
|
|
((b[59] >> 8) & 0xff), (b[59] & 0xff),
|
|
((b[60] >> 8) & 0xff), (b[60] & 0xff),
|
|
((b[61] >> 8) & 0xff), (b[61] & 0xff),
|
|
((b[62] >> 8) & 0xff), (b[62] & 0xff));
|
|
vp++;
|
|
} else {
|
|
if (sromrev >= 1){
|
|
/* Word 60 OFDM tx power offset from CCK level */
|
|
/* OFDM Power Offset - opo */
|
|
w = b[60] & 0xff;
|
|
if (w == 0xff)
|
|
w = 16;
|
|
vp += sprintf(vp, "opo=%d", w);
|
|
vp++;
|
|
}
|
|
}
|
|
|
|
/* final nullbyte terminator */
|
|
*vp++ = '\0';
|
|
|
|
c = vp - base;
|
|
ASSERT(c <= VARS_MAX);
|
|
|
|
if (c == VARS_MAX) {
|
|
*vars = base;
|
|
} else {
|
|
vp = MALLOC(c);
|
|
ASSERT(vp);
|
|
bcopy(base, vp, c);
|
|
MFREE(base, VARS_MAX);
|
|
*vars = vp;
|
|
}
|
|
*count = c;
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Read the cis and call parsecis to initialize the vars.
|
|
* Return 0 on success, nonzero on error.
|
|
*/
|
|
static int
|
|
initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count)
|
|
{
|
|
uint8 *cis = NULL;
|
|
int rc;
|
|
uint data_sz;
|
|
|
|
data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
|
|
|
|
if ((cis = MALLOC(data_sz)) == NULL)
|
|
return (-1);
|
|
|
|
if (sb_pcmciarev(sbh) == 1) {
|
|
if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
|
|
MFREE(cis, data_sz);
|
|
return (-1);
|
|
}
|
|
/* fix up endianess for 16-bit data vs 8-bit parsing */
|
|
ltoh16_buf((uint16 *)cis, data_sz);
|
|
} else
|
|
OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
|
|
|
|
rc = srom_parsecis(cis, vars, count);
|
|
|
|
MFREE(cis, data_sz);
|
|
|
|
return (rc);
|
|
}
|
|
|