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git://projects.qi-hardware.com/openwrt-xburst.git
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fb189822fc
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15918 3c298f89-4303-0410-b956-a3cf2f4a3e73
468 lines
14 KiB
C
468 lines
14 KiB
C
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/*
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*
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* Copyright (c) 2004-2007 Atheros Communications Inc.
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* All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation;
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*
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* Software distributed under the License is distributed on an "AS
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* IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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* implied. See the License for the specific language governing
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* rights and limitations under the License.
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*
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*
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*
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*/
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#include "a_config.h"
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#include "athdefs.h"
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#include "a_types.h"
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#include "AR6Khwreg.h"
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#include "targaddrs.h"
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#include "a_osapi.h"
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#include "hif.h"
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#include "htc_api.h"
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#include "bmi.h"
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#include "bmi_msg.h"
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#include "common_drv.h"
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#include "a_debug.h"
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#include "targaddrs.h"
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#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
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(((TargetType) == TARGET_TYPE_AR6001) ? \
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AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
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AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
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/* Compile the 4BYTE version of the window register setup routine,
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* This mitigates host interconnect issues with non-4byte aligned bus requests, some
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* interconnects use bus adapters that impose strict limitations.
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* Since diag window access is not intended for performance critical operations, the 4byte mode should
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* be satisfactory even though it generates 4X the bus activity. */
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#ifdef USE_4BYTE_REGISTER_ACCESS
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/* set the window address register (using 4-byte register access ). */
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A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
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{
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A_STATUS status;
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A_UINT8 addrValue[4];
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int i;
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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for (i = 1; i <= 3; i++) {
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/* fill the buffer with the address byte value we want to hit 4 times*/
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addrValue[0] = ((A_UINT8 *)&Address)[i];
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addrValue[1] = addrValue[0];
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addrValue[2] = addrValue[0];
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addrValue[3] = addrValue[0];
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/* hit each byte of the register address with a 4-byte write operation to the same address,
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* this is a harmless operation */
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status = HIFReadWrite(hifDevice,
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RegisterAddr+i,
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addrValue,
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4,
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HIF_WR_SYNC_BYTE_FIX,
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NULL);
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if (status != A_OK) {
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break;
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}
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}
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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/* write the address register again, this time write the whole 4-byte value.
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* The effect here is that the LSB write causes the cycle to start, the extra
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* 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
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status = HIFReadWrite(hifDevice,
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RegisterAddr,
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(A_UCHAR *)(&Address),
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4,
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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return A_OK;
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}
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#else
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/* set the window address register */
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A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
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{
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A_STATUS status;
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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status = HIFReadWrite(hifDevice,
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RegisterAddr+1, /* write upper 3 bytes */
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((A_UCHAR *)(&Address))+1,
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sizeof(A_UINT32)-1,
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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/* write the LSB of the register, this initiates the operation */
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status = HIFReadWrite(hifDevice,
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RegisterAddr,
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(A_UCHAR *)(&Address),
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sizeof(A_UINT8),
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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return A_OK;
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}
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#endif
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/*
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* Read from the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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*/
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A_STATUS
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ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
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{
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A_STATUS status;
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/* set window register to start read cycle */
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status = ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_READ_ADDR_ADDRESS,
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*address);
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if (status != A_OK) {
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return status;
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}
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/* read the data */
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status = HIFReadWrite(hifDevice,
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WINDOW_DATA_ADDRESS,
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(A_UCHAR *)data,
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sizeof(A_UINT32),
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
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return status;
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}
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return status;
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}
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/*
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* Write to the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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*/
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A_STATUS
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ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
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{
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A_STATUS status;
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/* set write data */
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status = HIFReadWrite(hifDevice,
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WINDOW_DATA_ADDRESS,
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(A_UCHAR *)data,
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sizeof(A_UINT32),
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
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return status;
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}
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/* set window register, which starts the write cycle */
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return ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_WRITE_ADDR_ADDRESS,
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*address);
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}
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A_STATUS
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ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
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A_UCHAR *data, A_UINT32 length)
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{
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A_UINT32 count;
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A_STATUS status = A_OK;
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for (count = 0; count < length; count += 4, address += 4) {
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if ((status = ar6000_ReadRegDiag(hifDevice, &address,
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(A_UINT32 *)&data[count])) != A_OK)
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{
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break;
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}
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}
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return status;
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}
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A_STATUS
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ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
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A_UCHAR *data, A_UINT32 length)
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{
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A_UINT32 count;
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A_STATUS status = A_OK;
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for (count = 0; count < length; count += 4, address += 4) {
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if ((status = ar6000_WriteRegDiag(hifDevice, &address,
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(A_UINT32 *)&data[count])) != A_OK)
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{
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break;
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}
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}
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return status;
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}
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A_STATUS
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ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice)
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{
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int i;
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struct forceROM_s {
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A_UINT32 addr;
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A_UINT32 data;
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};
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struct forceROM_s *ForceROM;
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int szForceROM;
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A_UINT32 instruction;
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static struct forceROM_s ForceROM_REV2[] = {
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/* NB: This works for old REV2 ROM (old). */
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{0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */
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{0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */
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{MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */
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{MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */
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{MC_REMAP_SIZE_ADDRESS, 0x00000000}, /* ...1 cache line */
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{MC_REMAP_VALID_ADDRESS, 0x00000001}, /* ...remap is valid */
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{LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
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{RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
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};
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static struct forceROM_s ForceROM_NEW[] = {
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/* NB: This works for AR6000 ROM REV3 and beyond. */
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{LOCAL_SCRATCH_ADDRESS, AR6K_OPTION_IGNORE_FLASH},
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{LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
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{RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
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};
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/*
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* Examine a semi-arbitrary instruction that's different
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* in REV2 and other revisions.
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* NB: If a Host port does not require simultaneous support
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* for multiple revisions of Target ROM, this code can be elided.
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*/
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(void)ar6000_ReadDataDiag(hifDevice, 0x01000040,
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(A_UCHAR *)&instruction, 4);
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("instruction=0x%x\n", instruction));
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if (instruction == 0x3c1aa200) {
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/* It's an old ROM */
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ForceROM = ForceROM_REV2;
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szForceROM = sizeof(ForceROM_REV2)/sizeof(*ForceROM);
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using OLD method\n"));
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} else {
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ForceROM = ForceROM_NEW;
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szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using NEW method\n"));
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}
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Force Target to execute from ROM....\n"));
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for (i = 0; i < szForceROM; i++)
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{
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if (ar6000_WriteRegDiag(hifDevice,
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&ForceROM[i].addr,
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&ForceROM[i].data) != A_OK)
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{
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
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return A_ERROR;
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}
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}
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msleep(50); /* delay to allow dragon to come to BMI phase */
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return A_OK;
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}
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/* reset device */
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A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
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{
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#if !defined(DWSIM)
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A_STATUS status = A_OK;
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A_UINT32 address;
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A_UINT32 data;
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do {
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// address = RESET_CONTROL_ADDRESS;
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data = RESET_CONTROL_COLD_RST_MASK;
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/* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
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if (TargetType == TARGET_TYPE_AR6001) {
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address = 0x0C000000;
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} else {
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if (TargetType == TARGET_TYPE_AR6002) {
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address = 0x00004000;
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} else {
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A_ASSERT(0);
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}
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}
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status = ar6000_WriteRegDiag(hifDevice, &address, &data);
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if (A_FAILED(status)) {
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break;
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}
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/*
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* Read back the RESET CAUSE register to ensure that the cold reset
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* went through.
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*/
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msleep(2000); /* 2 second delay to allow things to settle down */
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// address = RESET_CAUSE_ADDRESS;
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/* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
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if (TargetType == TARGET_TYPE_AR6001) {
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address = 0x0C0000CC;
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} else {
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if (TargetType == TARGET_TYPE_AR6002) {
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address = 0x000040C0;
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} else {
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A_ASSERT(0);
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}
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}
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data = 0;
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status = ar6000_ReadRegDiag(hifDevice, &address, &data);
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if (A_FAILED(status)) {
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break;
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}
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
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data &= RESET_CAUSE_LAST_MASK;
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if (data != 2) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
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}
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} while (FALSE);
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if (A_FAILED(status)) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
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}
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#endif
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return A_OK;
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}
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#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR6001_regdump.h */
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#define REG_DUMP_COUNT_AR6002 32 /* WORDs, derived from AR6002_regdump.h */
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#if REG_DUMP_COUNT_AR6001 <= REG_DUMP_COUNT_AR6002
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#define REGISTER_DUMP_LEN_MAX REG_DUMP_COUNT_AR6002
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#else
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#define REGISTER_DUMP_LEN_MAX REG_DUMP_COUNT_AR6001
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#endif
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void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
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{
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A_UINT32 address;
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A_UINT32 regDumpArea = 0;
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A_STATUS status;
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A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
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A_UINT32 regDumpCount = 0;
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A_UINT32 i;
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do {
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/* the reg dump pointer is copied to the host interest area */
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address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
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if (TargetType == TARGET_TYPE_AR6001) {
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/* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
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* this may be fixed in later firmware versions */
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address = 0x18a0;
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regDumpCount = REG_DUMP_COUNT_AR6001;
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} else if (TargetType == TARGET_TYPE_AR6002) {
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regDumpCount = REG_DUMP_COUNT_AR6002;
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} else {
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A_ASSERT(0);
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}
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/* read RAM location through diagnostic window */
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status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea);
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if (A_FAILED(status)) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
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break;
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}
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
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if (regDumpArea == 0) {
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/* no reg dump */
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break;
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}
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if (TargetType == TARGET_TYPE_AR6001) {
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regDumpArea &= 0x0FFFFFFF; /* convert to physical address in target memory */
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}
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/* fetch register dump data */
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status = ar6000_ReadDataDiag(hifDevice,
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regDumpArea,
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(A_UCHAR *)®DumpValues[0],
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regDumpCount * (sizeof(A_UINT32)));
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if (A_FAILED(status)) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
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break;
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}
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
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for (i = 0; i < regDumpCount; i++) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
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}
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} while (FALSE);
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}
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