mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-29 17:56:26 +02:00
343c185b7d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16547 3c298f89-4303-0410-b956-a3cf2f4a3e73
131 lines
5.1 KiB
Diff
131 lines
5.1 KiB
Diff
From b6b6d18a54e22784cb48e1953201484830d030e4 Mon Sep 17 00:00:00 2001
|
|
From: Kurt Mahan <kmahan@freescale.com>
|
|
Date: Thu, 6 Dec 2007 14:17:46 -0700
|
|
Subject: [PATCH] Change USB to SDRAM priority.
|
|
|
|
Increase the USB priority to the maximum, above ColdfireCore,
|
|
in the SDRAM crossbar switch. This fixes the issues with the
|
|
USB core not being able to transfer to memory fast enough to
|
|
keep up with HS.
|
|
|
|
LTIBName: m5445x-usb-sdram-priority
|
|
Signed-off-by: Kurt Mahan <kmahan@freescale.com>
|
|
---
|
|
arch/m68k/coldfire/config.c | 12 ++++++
|
|
include/asm-m68k/mcf5445x_xbs.h | 81 +++++++++++++++++++++++++++++++++++++++
|
|
2 files changed, 93 insertions(+), 0 deletions(-)
|
|
create mode 100644 include/asm-m68k/mcf5445x_xbs.h
|
|
|
|
--- a/arch/m68k/coldfire/config.c
|
|
+++ b/arch/m68k/coldfire/config.c
|
|
@@ -36,6 +36,7 @@
|
|
#include <asm/mcf5445x_sdramc.h>
|
|
#include <asm/mcf5445x_fbcs.h>
|
|
#include <asm/mcf5445x_dtim.h>
|
|
+#include <asm/mcf5445x_xbs.h>
|
|
|
|
/* JKM -- testing */
|
|
#include <linux/pfn.h>
|
|
@@ -131,6 +132,17 @@ asmlinkage void __init cf_early_init(voi
|
|
MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
|
|
#endif
|
|
|
|
+ /* Setup SDRAM crossbar(XBS) priorities */
|
|
+printk(KERN_INFO "Bumping USB Priority\n");
|
|
+ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
|
|
+ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
|
|
+ MCF_XBS_PRS_M2(MCF_XBS_PRI_4) |
|
|
+ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) |
|
|
+ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) |
|
|
+ MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
|
|
+ MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
|
|
+
|
|
+
|
|
m68k_machtype = MACH_CFMMU;
|
|
m68k_fputype = FPU_CFV4E;
|
|
m68k_mmutype = MMU_CFV4E;
|
|
--- /dev/null
|
|
+++ b/include/asm-m68k/mcf5445x_xbs.h
|
|
@@ -0,0 +1,81 @@
|
|
+/*
|
|
+ * Kurt Mahan kmahan@freescale.com
|
|
+ *
|
|
+ * Copyright Freescale Semiconductor, Inc. 2007
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ */
|
|
+
|
|
+#ifndef __MCF5445X_XBS_H__
|
|
+#define __MCF5445X_XBS_H__
|
|
+
|
|
+/*
|
|
+ * Crossbar Switch (XBS)
|
|
+ */
|
|
+
|
|
+/* Register read/write macros */
|
|
+#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
|
|
+#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
|
|
+#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
|
|
+#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
|
|
+#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
|
|
+#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */
|
|
+#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */
|
|
+#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
|
|
+#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */
|
|
+#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */
|
|
+#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
|
|
+#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
|
|
+#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
|
|
+#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
|
|
+
|
|
+/* Priorities */
|
|
+#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
|
|
+#define MCF_XBS_PRI_2 1 /* Level 2 */
|
|
+#define MCF_XBS_PRI_3 2 /* Level 3 */
|
|
+#define MCF_XBS_PRI_4 3 /* Level 4 */
|
|
+#define MCF_XBS_PRI_5 4 /* Level 5 */
|
|
+#define MCF_XBS_PRI_6 5 /* Level 6 */
|
|
+#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
|
|
+#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
|
|
+
|
|
+/* Priority Register (PRSn) Defs */
|
|
+#define MCF_XBS_PRS_MACRO(m,p) ((p)<<((m)<<2))
|
|
+#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
|
|
+#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
|
|
+#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
|
|
+#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
|
|
+#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
|
|
+#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
|
|
+#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
|
|
+#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
|
|
+
|
|
+/* Control Register (CRSn) Defs */
|
|
+#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
|
|
+#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
|
|
+#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
|
|
+#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
|
|
+
|
|
+/* MCF_XBS_CRS_ARB Defs */
|
|
+#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
|
|
+#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
|
|
+
|
|
+/* MCF_XBS_CRS_PCTL Defs */
|
|
+#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
|
|
+#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
|
|
+#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
|
|
+
|
|
+/* MCF_XBS_CRS_PARK Defs */
|
|
+#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
|
|
+#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
|
|
+#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
|
|
+#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
|
|
+#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
|
|
+#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
|
|
+#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
|
|
+#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
|
|
+
|
|
+#endif /* __MCF5445X_XBS_H__ */
|