mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 13:39:42 +02:00
3a02e3c605
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14953 3c298f89-4303-0410-b956-a3cf2f4a3e73
569 lines
15 KiB
C
569 lines
15 KiB
C
#ifndef BCM63XX_CPU_H_
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#define BCM63XX_CPU_H_
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#include <linux/types.h>
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#include <linux/init.h>
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#include <bcm63xx_regs.h>
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/*
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* Macro to fetch bcm63xx cpu id and revision, should be optimized at
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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void __init bcm63xx_cpu_init(void);
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u16 __bcm63xx_get_cpu_id(void);
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u16 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_6338
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
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# endif
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# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
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#else
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# define BCMCPU_IS_6338() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
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# endif
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# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
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#else
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# define BCMCPU_IS_6345() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
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# endif
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# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
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#else
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# define BCMCPU_IS_6348() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
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# endif
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# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
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#else
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# define BCMCPU_IS_6358() (0)
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#endif
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#ifndef bcm63xx_get_cpu_id
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#error "No CPU support configured"
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#endif
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/*
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* While registers sets are (mostly) the same across 63xx CPU, base
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* address of these sets do change.
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*/
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enum bcm63xx_regs_set {
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RSET_DSL_LMEM = 0,
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RSET_PERF,
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RSET_TIMER,
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RSET_WDT,
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RSET_UART0,
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RSET_GPIO,
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RSET_SPI,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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RSET_USBH_PRIV,
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RSET_MPI,
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RSET_PCMCIA,
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RSET_DSL,
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RSET_ENET0,
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RSET_ENET1,
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RSET_ENETDMA,
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RSET_EHCI0,
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RSET_SDRAM,
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RSET_MEMC,
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RSET_DDR,
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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#define RSET_DSL_SIZE 4096
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#define RSET_WDT_SIZE 12
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_UART_SIZE 24
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#define RSET_SPI_SIZE 256
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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#define RSET_PCMCIA_SIZE 12
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/*
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* 6338 register sets base address
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*/
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#define BCM_6338_PERF_BASE (0xfffe0000)
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#define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
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#define BCM_6338_TIMER_BASE (0xfffe0200)
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#define BCM_6338_WDT_BASE (0xfffe021c)
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#define BCM_6338_UART0_BASE (0xfffe0300)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_SAR_BASE (0xfffe2000)
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#define BCM_6338_ENETDMA_BASE (0xfffe2400)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_ENET0_BASE (0xfffe2800)
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#define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
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#define BCM_6338_MEMC_BASE (0xfffe3100)
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/*
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* 6345 register sets base address
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*/
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#define BCM_6345_PERF_BASE (0xfffe0000)
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#define BCM_6345_TIMER_BASE (0xfffe0200)
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#define BCM_6345_WDT_BASE (0xfffe021c)
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#define BCM_6345_UART0_BASE (0xfffe0300)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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/*
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* 6348 register sets base address
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*/
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#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6348_PERF_BASE (0xfffe0000)
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#define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */
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#define BCM_6348_TIMER_BASE (0xfffe0200)
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#define BCM_6348_WDT_BASE (0xfffe021c)
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#define BCM_6348_UART0_BASE (0xfffe0300)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_USBDMA_BASE (0xfffe1400)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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#define BCM_6348_SAR_BASE (0xfffe4000)
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#define BCM_6348_UBUS_BASE (0xfffe5000)
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#define BCM_6348_ENET0_BASE (0xfffe6000)
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#define BCM_6348_ENET1_BASE (0xfffe6800)
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#define BCM_6348_ENETDMA_BASE (0xfffe7000)
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#define BCM_6348_EHCI0_BASE (0xdeadbeef)
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#define BCM_6348_SDRAM_BASE (0xfffe2300)
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#define BCM_6348_MEMC_BASE (0xdeadbeef)
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#define BCM_6348_DDR_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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*/
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#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6358_PERF_BASE (0xfffe0000)
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#define BCM_6358_TIMER_BASE (0xfffe0040)
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#define BCM_6358_WDT_BASE (0xfffe005c)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_UART0_BASE (0xfffe0100)
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#define BCM_6358_UDC0_BASE (0xfffe0400)
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#define BCM_6358_SPI_BASE (0xfffe0800)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6358_DSL_BASE (0xfffe3000)
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#define BCM_6358_ENET0_BASE (0xfffe4000)
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#define BCM_6358_ENET1_BASE (0xfffe4800)
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#define BCM_6358_ENETDMA_BASE (0xfffe5000)
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#define BCM_6358_EHCI0_BASE (0xfffe1300)
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#define BCM_6358_SDRAM_BASE (0xdeadbeef)
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#define BCM_6358_MEMC_BASE (0xfffe1200)
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#define BCM_6358_DDR_BASE (0xfffe12a0)
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extern const unsigned long *bcm63xx_regs_base;
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_base[set];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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switch (set) {
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case RSET_PERF:
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return BCM_6338_PERF_BASE;
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case RSET_TIMER:
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return BCM_6338_TIMER_BASE;
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case RSET_WDT:
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return BCM_6338_WDT_BASE;
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case RSET_UART0:
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return BCM_6338_UART0_BASE;
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case RSET_GPIO:
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return BCM_6338_GPIO_BASE;
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case RSET_SPI:
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return BCM_6338_SPI_BASE;
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case RSET_MEMC:
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return BCM_6338_MEMC_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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switch (set) {
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case RSET_PERF:
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return BCM_6345_PERF_BASE;
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case RSET_TIMER:
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return BCM_6345_TIMER_BASE;
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case RSET_WDT:
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return BCM_6345_WDT_BASE;
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case RSET_UART0:
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return BCM_6345_UART0_BASE;
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case RSET_GPIO:
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return BCM_6345_GPIO_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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switch (set) {
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case RSET_DSL_LMEM:
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return BCM_6348_DSL_LMEM_BASE;
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case RSET_PERF:
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return BCM_6348_PERF_BASE;
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case RSET_TIMER:
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return BCM_6348_TIMER_BASE;
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case RSET_WDT:
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return BCM_6348_WDT_BASE;
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case RSET_UART0:
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return BCM_6348_UART0_BASE;
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case RSET_GPIO:
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return BCM_6348_GPIO_BASE;
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case RSET_SPI:
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return BCM_6348_SPI_BASE;
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case RSET_UDC0:
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return BCM_6348_UDC0_BASE;
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case RSET_OHCI0:
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return BCM_6348_OHCI0_BASE;
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case RSET_OHCI_PRIV:
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return BCM_6348_OHCI_PRIV_BASE;
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case RSET_USBH_PRIV:
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return BCM_6348_USBH_PRIV_BASE;
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case RSET_MPI:
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return BCM_6348_MPI_BASE;
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case RSET_PCMCIA:
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return BCM_6348_PCMCIA_BASE;
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case RSET_DSL:
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return BCM_6348_DSL_BASE;
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case RSET_ENET0:
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return BCM_6348_ENET0_BASE;
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case RSET_ENET1:
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return BCM_6348_ENET1_BASE;
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case RSET_ENETDMA:
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return BCM_6348_ENETDMA_BASE;
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case RSET_EHCI0:
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return BCM_6348_EHCI0_BASE;
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case RSET_SDRAM:
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return BCM_6348_SDRAM_BASE;
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case RSET_MEMC:
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return BCM_6348_MEMC_BASE;
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case RSET_DDR:
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return BCM_6348_DDR_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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switch (set) {
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case RSET_DSL_LMEM:
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return BCM_6358_DSL_LMEM_BASE;
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case RSET_PERF:
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return BCM_6358_PERF_BASE;
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case RSET_TIMER:
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return BCM_6358_TIMER_BASE;
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case RSET_WDT:
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return BCM_6358_WDT_BASE;
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case RSET_UART0:
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return BCM_6358_UART0_BASE;
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case RSET_GPIO:
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return BCM_6358_GPIO_BASE;
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case RSET_SPI:
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return BCM_6358_SPI_BASE;
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case RSET_UDC0:
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return BCM_6358_UDC0_BASE;
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case RSET_OHCI0:
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return BCM_6358_OHCI0_BASE;
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case RSET_OHCI_PRIV:
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return BCM_6358_OHCI_PRIV_BASE;
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case RSET_USBH_PRIV:
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return BCM_6358_USBH_PRIV_BASE;
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case RSET_MPI:
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return BCM_6358_MPI_BASE;
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case RSET_PCMCIA:
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return BCM_6358_PCMCIA_BASE;
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case RSET_ENET0:
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return BCM_6358_ENET0_BASE;
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case RSET_ENET1:
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return BCM_6358_ENET1_BASE;
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case RSET_ENETDMA:
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return BCM_6358_ENETDMA_BASE;
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case RSET_DSL:
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return BCM_6358_DSL_BASE;
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case RSET_EHCI0:
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return BCM_6358_EHCI0_BASE;
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case RSET_SDRAM:
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return BCM_6358_SDRAM_BASE;
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case RSET_MEMC:
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return BCM_6358_MEMC_BASE;
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case RSET_DDR:
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return BCM_6358_DDR_BASE;
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}
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#endif
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#endif
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/* unreached */
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return 0;
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}
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/*
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* SPI register layout is not compatible
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* accross CPU versions but it is software
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* compatible
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*/
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enum bcm63xx_regs_spi {
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SPI_CMD,
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SPI_INT_STATUS,
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SPI_INT_MASK_ST,
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SPI_INT_MASK,
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SPI_ST,
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SPI_CLK_CFG,
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SPI_FILL_BYTE,
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SPI_MSG_TAIL,
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SPI_RX_TAIL,
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SPI_MSG_CTL,
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SPI_MSG_DATA,
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SPI_RX_DATA,
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};
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extern const unsigned long *bcm63xx_regs_spi;
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static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_spi[reg];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6338_SPI_CMD;
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case SPI_INT_STATUS:
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return SPI_BCM_6338_SPI_INT_STATUS;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6338_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6338_SPI_INT_MASK;
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case SPI_ST:
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return SPI_BCM_6338_SPI_ST;
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case SPI_CLK_CFG:
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return SPI_BCM_6338_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
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return SPI_BCM_6338_SPI_FILL_BYTE;
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case SPI_MSG_TAIL:
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return SPI_BCM_6338_SPI_MSG_TAIL;
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case SPI_RX_TAIL:
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return SPI_BCM_6338_SPI_RX_TAIL;
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case SPI_MSG_CTL:
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return SPI_BCM_6338_SPI_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6338_SPI_MSG_DATA;
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case SPI_RX_DATA:
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return SPI_BCM_6338_SPI_RX_DATA;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6348_SPI_CMD;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6348_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6348_SPI_INT_MASK;
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case SPI_INT_STATUS:
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return SPI_BCM_6348_SPI_INT_STATUS;
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case SPI_ST:
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return SPI_BCM_6348_SPI_ST;
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case SPI_CLK_CFG:
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return SPI_BCM_6348_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
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return SPI_BCM_6348_SPI_FILL_BYTE;
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case SPI_MSG_TAIL:
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return SPI_BCM_6348_SPI_MSG_TAIL;
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case SPI_RX_TAIL:
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return SPI_BCM_6348_SPI_RX_TAIL;
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case SPI_MSG_CTL:
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return SPI_BCM_6348_SPI_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6348_SPI_MSG_DATA;
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case SPI_RX_DATA:
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return SPI_BCM_6348_SPI_RX_DATA;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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switch (reg) {
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case SPI_CMD:
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return SPI_BCM_6358_SPI_CMD;
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case SPI_INT_STATUS:
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return SPI_BCM_6358_SPI_INT_STATUS;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6358_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6358_SPI_INT_MASK;
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case SPI_ST:
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return SPI_BCM_6358_SPI_STATUS;
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case SPI_CLK_CFG:
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return SPI_BCM_6358_SPI_CLK_CFG;
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case SPI_FILL_BYTE:
|
|
return SPI_BCM_6358_SPI_FILL_BYTE;
|
|
case SPI_MSG_TAIL:
|
|
return SPI_BCM_6358_SPI_MSG_TAIL;
|
|
case SPI_RX_TAIL:
|
|
return SPI_BCM_6358_SPI_RX_TAIL;
|
|
case SPI_MSG_CTL:
|
|
return SPI_BCM_6358_MSG_CTL;
|
|
case SPI_MSG_DATA:
|
|
return SPI_BCM_6358_SPI_MSG_DATA;
|
|
case SPI_RX_DATA:
|
|
return SPI_BCM_6358_SPI_RX_DATA;
|
|
}
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* IRQ number changes across CPU too
|
|
*/
|
|
enum bcm63xx_irq {
|
|
IRQ_TIMER = 0,
|
|
IRQ_UART0,
|
|
IRQ_SPI,
|
|
IRQ_DSL,
|
|
IRQ_UDC0,
|
|
IRQ_ENET0,
|
|
IRQ_ENET1,
|
|
IRQ_ENET_PHY,
|
|
IRQ_OHCI0,
|
|
IRQ_EHCI0,
|
|
IRQ_PCMCIA0,
|
|
IRQ_ENET0_RXDMA,
|
|
IRQ_ENET0_TXDMA,
|
|
IRQ_ENET1_RXDMA,
|
|
IRQ_ENET1_TXDMA,
|
|
IRQ_PCI,
|
|
IRQ_PCMCIA,
|
|
};
|
|
|
|
/*
|
|
* 6338 irqs
|
|
*/
|
|
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
|
|
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
|
#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
|
|
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
|
|
#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
|
|
#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
|
|
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
|
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
|
#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
|
|
#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
|
|
#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
|
|
#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
|
|
#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
|
|
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
|
#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
|
|
#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
|
|
|
|
/*
|
|
* 6345 irqs
|
|
*/
|
|
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
|
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
|
|
#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
|
|
#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
|
|
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
|
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
|
|
|
|
/*
|
|
* 6348 irqs
|
|
*/
|
|
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
|
|
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
|
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
|
|
#define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
|
|
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
|
|
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
|
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
|
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
|
|
#define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
|
|
#define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
|
|
#define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
|
|
#define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
|
|
#define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
|
|
#define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
|
|
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
|
|
#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
|
|
#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
|
|
#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
|
|
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
|
|
#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
|
|
|
|
/*
|
|
* 6358 irqs
|
|
*/
|
|
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
|
#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
|
|
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
|
|
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
|
|
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
|
|
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
|
|
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
|
|
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
|
|
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
|
|
#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
|
|
#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
|
|
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
|
|
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
|
|
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
|
|
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
|
|
|
|
extern const int *bcm63xx_irqs;
|
|
|
|
static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
|
|
{
|
|
return bcm63xx_irqs[irq];
|
|
}
|
|
|
|
/*
|
|
* return installed memory size
|
|
*/
|
|
unsigned int bcm63xx_get_memory_size(void);
|
|
|
|
#endif /* !BCM63XX_CPU_H_ */
|