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e13225ef04
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16246 3c298f89-4303-0410-b956-a3cf2f4a3e73
71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From: Catalin Marinas <catalin.marinas@arm.com>
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Date: Sat, 30 May 2009 13:00:18 +0000 (+0100)
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Subject: Fix the VFP handling on the Feroceon CPU
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X-Git-Url: http://www.linux-arm.org/git?p=linux-2.6.git;a=commitdiff_plain;h=85d6943af50537d3aec58b967ffbd3fec88453e9;hp=26584853a44c58f3d6ac7360d697a2ddcd1a3efa
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Fix the VFP handling on the Feroceon CPU
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This CPU generates synchronous VFP exceptions in a non-standard way -
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the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the
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VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP
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subarchitecture 2. The main problem is that the faulty instruction
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(which needs to be emulated in software) will be restarted several times
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(normally until a context switch disables the VFP). This patch ensures
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that the VFP exception is treated as synchronous.
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Cc: Nicolas Pitre <nico@cam.org>
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---
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--- a/arch/arm/vfp/vfphw.S
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+++ b/arch/arm/vfp/vfphw.S
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@@ -100,6 +100,7 @@ ENTRY(vfp_support_entry)
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beq no_old_VFP_process
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VFPFSTMIA r4, r5 @ save the working registers
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VFPFMRX r5, FPSCR @ current status
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+#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
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@@ -107,6 +108,7 @@ ENTRY(vfp_support_entry)
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beq 1f
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VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
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1:
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+#endif
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ start of the register dump
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@@ -119,6 +121,7 @@ no_old_VFP_process:
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VFPFLDMIA r10, r5 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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+#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to restore?
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beq 1f
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VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
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@@ -126,6 +129,7 @@ no_old_VFP_process:
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beq 1f
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VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
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1:
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+#endif
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VFPFMXR FPSCR, r5 @ restore status
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check_for_exception:
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--- a/arch/arm/vfp/vfpmodule.c
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+++ b/arch/arm/vfp/vfpmodule.c
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@@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc,
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}
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if (fpexc & FPEXC_EX) {
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+#ifndef CONFIG_CPU_FEROCEON
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/*
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* Asynchronous exception. The instruction is read from FPINST
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* and the interrupted instruction has to be restarted.
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*/
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trigger = fmrx(FPINST);
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regs->ARM_pc -= 4;
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+#endif
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} else if (!(fpexc & FPEXC_DEX)) {
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/*
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* Illegal combination of bits. It can be caused by an
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