mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 11:35:52 +03:00
63d3f006df
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33889 3c298f89-4303-0410-b956-a3cf2f4a3e73
510 lines
18 KiB
Diff
510 lines
18 KiB
Diff
[PATCH] MIPS: BCM63XX: enable ethernet for BCM6345
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BCM6345 has a slightly older DMA engine which is not supported by default by
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the bcm63xx_enet driver. This patch adds the missing Ethernet DMA definitions
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as well as patches all the places in the ethernet driver were the DMA
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reading/writing is different.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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--- a/arch/mips/bcm63xx/dev-enet.c
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+++ b/arch/mips/bcm63xx/dev-enet.c
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@@ -172,7 +172,7 @@ int __init bcm63xx_enet_register(int uni
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if (unit > 1)
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return -ENODEV;
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- if (unit == 1 && BCMCPU_IS_6338())
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+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
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return -ENODEV;
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ret = register_shared();
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -764,6 +764,37 @@
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/* State Ram Word 4 */
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#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
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+/* Broadcom 6345 ENET DMA definitions */
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+#define ENETDMA_6345_CHANCFG_REG(x) (0x00 + (x) * 0x40)
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+#define ENETDMA_6345_CHANCFG_EN_SHIFT 0
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+#define ENETDMA_6345_CHANCFG_EN_MASK (1 << ENETDMA_6345_CHANCFG_EN_SHIFT)
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+#define ENETDMA_6345_PKTHALT_SHIFT 1
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+#define ENETDMA_6345_PKTHALT_MASK (1 << ENETDMA_6345_PKTHALT_SHIFT)
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+#define ENETDMA_6345_CHAINING_SHIFT 2
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+#define ENETDMA_6345_CHAINING_MASK (1 << ENETDMA_6345_CHAINING_SHIFT)
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+#define ENETDMA_6345_WRAP_EN_SHIFT 3
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+#define ENETDMA_6345_WRAP_EN_MASK (1 << ENETDMA_6345_WRAP_EN_SHIFT)
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+#define ENETDMA_6345_FLOWC_EN_SHIFT 4
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+#define ENETDMA_6345_FLOWC_EN_MASK (1 << ENETDMA_6345_FLOWC_EN_SHIFT)
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+
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+#define ENETDMA_6345_MAXBURST_REG(x) (0x04 + (x) * 0x40)
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+
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+#define ENETDMA_6345_RSTART_REG(x) (0x08 + (x) * 0x40)
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+
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+#define ENETDMA_6345_LEN_REG(x) (0x0C + (x) * 0x40)
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+
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+#define ENETDMA_6345_BSTAT_REG(x) (0x10 + (x) * 0x40)
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+
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+#define ENETDMA_6345_IR_REG(x) (0x14 + (x) * 0x40)
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+#define ENETDMA_6345_IR_BUFDONE_MASK (1 << 0)
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+#define ENETDMA_6345_IR_PKTDONE_MASK (1 << 1)
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+#define ENETDMA_6345_IR_NOTOWNER_MASK (1 << 2)
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+
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+#define ENETDMA_6345_IRMASK_REG(x) (0x18 + (x) * 0x40)
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+
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+#define ENETDMA_6345_FC_REG(x) (0x1C + (x) * 0x40)
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+
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+#define ENETDMA_6345_BUFALLOC_REG(x) (0x20 + (x) * 0x40)
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/*************************************************************************
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* _REG relative to RSET_ENETDMAC
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--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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@@ -32,6 +32,7 @@
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#include <linux/if_vlan.h>
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#include <bcm63xx_dev_enet.h>
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+#include <bcm63xx_cpu.h>
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#include "bcm63xx_enet.h"
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static char bcm_enet_driver_name[] = "bcm63xx_enet";
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@@ -243,6 +244,7 @@ static void bcm_enet_mdio_write_mii(stru
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static int bcm_enet_refill_rx(struct net_device *dev)
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{
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struct bcm_enet_priv *priv;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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@@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
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len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
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len_stat |= DMADESC_OWNER_MASK;
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if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
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- len_stat |= DMADESC_WRAP_MASK;
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+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
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priv->rx_dirty_desc = 0;
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} else {
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priv->rx_dirty_desc++;
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@@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
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priv->rx_desc_count++;
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/* tell dma engine we allocated one buffer */
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- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ else
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+ enet_dma_writel(priv, 1, ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
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}
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/* If rx ring is still empty, set a timer to try allocating
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@@ -319,6 +324,7 @@ static int bcm_enet_receive_queue(struct
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struct bcm_enet_priv *priv;
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struct device *kdev;
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int processed;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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kdev = &priv->pdev->dev;
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@@ -357,7 +363,7 @@ static int bcm_enet_receive_queue(struct
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/* if the packet does not have start of packet _and_
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* end of packet flag set, then just recycle it */
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- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
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+ if ((len_stat & (DMADESC_ESOP_MASK >> desc_shift)) != (DMADESC_ESOP_MASK >> desc_shift)) {
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dev->stats.rx_dropped++;
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continue;
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}
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@@ -418,8 +424,15 @@ static int bcm_enet_receive_queue(struct
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bcm_enet_refill_rx(dev);
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/* kick rx dma */
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- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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- ENETDMAC_CHANCFG_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
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+ else
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+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
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+ ENETDMA_6345_CHAINING_MASK |
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+ ENETDMA_6345_WRAP_EN_MASK |
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+ ENETDMA_6345_FLOWC_EN_MASK,
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+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
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}
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return processed;
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@@ -494,10 +507,21 @@ static int bcm_enet_poll(struct napi_str
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dev = priv->net_dev;
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/* ack interrupts */
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- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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- ENETDMAC_IR_REG(priv->rx_chan));
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- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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- ENETDMAC_IR_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IR_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IR_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IR_REG(priv->tx_chan));
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+ }
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/* reclaim sent skb */
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tx_work_done = bcm_enet_tx_reclaim(dev, 0);
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@@ -516,10 +540,21 @@ static int bcm_enet_poll(struct napi_str
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napi_complete(napi);
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/* restore rx/tx interrupt */
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- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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- ENETDMAC_IRMASK_REG(priv->rx_chan));
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- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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- ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
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+ ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
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+ }
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return rx_work_done;
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}
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@@ -562,8 +597,13 @@ static irqreturn_t bcm_enet_isr_dma(int
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priv = netdev_priv(dev);
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/* mask rx/tx interrupts */
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- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
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+ }
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napi_schedule(&priv->napi);
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@@ -579,6 +619,7 @@ static int bcm_enet_start_xmit(struct sk
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struct bcm_enet_desc *desc;
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u32 len_stat;
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int ret;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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@@ -624,14 +665,14 @@ static int bcm_enet_start_xmit(struct sk
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DMA_TO_DEVICE);
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len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
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- len_stat |= DMADESC_ESOP_MASK |
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+ len_stat |= (DMADESC_ESOP_MASK >> desc_shift) |
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DMADESC_APPEND_CRC |
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DMADESC_OWNER_MASK;
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priv->tx_curr_desc++;
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if (priv->tx_curr_desc == priv->tx_ring_size) {
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priv->tx_curr_desc = 0;
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- len_stat |= DMADESC_WRAP_MASK;
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+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
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}
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priv->tx_desc_count--;
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@@ -642,8 +683,15 @@ static int bcm_enet_start_xmit(struct sk
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wmb();
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/* kick tx dma */
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- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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- ENETDMAC_CHANCFG_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
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+ ENETDMAC_CHANCFG_REG(priv->tx_chan));
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+ else
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+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
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+ ENETDMA_6345_CHAINING_MASK |
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+ ENETDMA_6345_WRAP_EN_MASK |
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+ ENETDMA_6345_FLOWC_EN_MASK,
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+ ENETDMA_6345_CHANCFG_REG(priv->tx_chan));
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/* stop queue if no more desc available */
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if (!priv->tx_desc_count)
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@@ -771,6 +819,9 @@ static void bcm_enet_set_flow(struct bcm
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val &= ~ENET_RXCFG_ENFLOW_MASK;
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enet_writel(priv, val, ENET_RXCFG_REG);
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+ if (BCMCPU_IS_6345())
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+ return;
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+
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/* tx flow control (pause frame generation) */
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val = enet_dma_readl(priv, ENETDMA_CFG_REG);
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if (tx_en)
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@@ -886,8 +937,13 @@ static int bcm_enet_open(struct net_devi
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/* mask all interrupts and request them */
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enet_writel(priv, 0, ENET_IRMASK_REG);
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- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
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+ }
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ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
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if (ret)
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@@ -966,8 +1022,12 @@ static int bcm_enet_open(struct net_devi
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priv->rx_curr_desc = 0;
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/* initialize flow control buffer allocation */
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- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
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- ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
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+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ else
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+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
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+ ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
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if (bcm_enet_refill_rx(dev)) {
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dev_err(kdev, "cannot allocate rx skb queue\n");
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@@ -976,37 +1036,62 @@ static int bcm_enet_open(struct net_devi
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}
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/* write rx & tx ring addresses */
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- enet_dmas_writel(priv, priv->rx_desc_dma,
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- ENETDMAS_RSTART_REG(priv->rx_chan));
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- enet_dmas_writel(priv, priv->tx_desc_dma,
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmas_writel(priv, priv->rx_desc_dma,
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+ ENETDMAS_RSTART_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, priv->tx_desc_dma,
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ENETDMAS_RSTART_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, priv->rx_desc_dma,
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+ ENETDMA_6345_RSTART_REG(priv->rx_chan));
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+ enet_dma_writel(priv, priv->tx_desc_dma,
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+ ENETDMA_6345_RSTART_REG(priv->tx_chan));
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+ }
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/* clear remaining state ram for rx & tx channel */
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
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- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
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+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->tx_chan));
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+ }
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/* set max rx/tx length */
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enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
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enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
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/* set dma maximum burst len */
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- enet_dmac_writel(priv, priv->dma_maxburst,
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- ENETDMAC_MAXBURST_REG(priv->rx_chan));
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- enet_dmac_writel(priv, priv->dma_maxburst,
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- ENETDMAC_MAXBURST_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dmac_writel(priv, priv->dma_maxburst,
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+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
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+ enet_dmac_writel(priv, priv->dma_maxburst,
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+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
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+ ENETDMA_6345_MAXBURST_REG(priv->rx_chan));
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+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
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+ ENETDMA_6345_MAXBURST_REG(priv->tx_chan));
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+ }
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/* set correct transmit fifo watermark */
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enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
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/* set flow control low/high threshold to 1/3 / 2/3 */
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- val = priv->rx_ring_size / 3;
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- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
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- val = (priv->rx_ring_size * 2) / 3;
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- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ val = priv->rx_ring_size / 3;
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+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
|
|
+ val = (priv->rx_ring_size * 2) / 3;
|
|
+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
|
|
+ } else {
|
|
+ enet_dma_writel(priv, 5, ENETDMA_6345_FC_REG(priv->rx_chan));
|
|
+ enet_dma_writel(priv, priv->rx_ring_size, ENETDMA_6345_LEN_REG(priv->rx_chan));
|
|
+ enet_dma_writel(priv, priv->tx_ring_size, ENETDMA_6345_LEN_REG(priv->tx_chan));
|
|
+ }
|
|
|
|
/* all set, enable mac and interrupts, start dma engine and
|
|
* kick rx dma channel */
|
|
@@ -1014,27 +1099,57 @@ static int bcm_enet_open(struct net_devi
|
|
val = enet_readl(priv, ENET_CTL_REG);
|
|
val |= ENET_CTL_ENABLE_MASK;
|
|
enet_writel(priv, val, ENET_CTL_REG);
|
|
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
|
|
- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
|
|
- ENETDMAC_CHANCFG_REG(priv->rx_chan));
|
|
+ if (!BCMCPU_IS_6345()) {
|
|
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
|
|
+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
|
|
+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
|
|
+ } else {
|
|
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
|
|
+ ENETDMA_6345_CHAINING_MASK |
|
|
+ ENETDMA_6345_WRAP_EN_MASK |
|
|
+ ENETDMA_6345_FLOWC_EN_MASK,
|
|
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
|
|
+ }
|
|
|
|
/* watch "mib counters about to overflow" interrupt */
|
|
enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
|
|
enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
|
|
|
|
/* watch "packet transferred" interrupt in rx and tx */
|
|
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
- ENETDMAC_IR_REG(priv->rx_chan));
|
|
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
- ENETDMAC_IR_REG(priv->tx_chan));
|
|
+ if (!BCMCPU_IS_6345()) {
|
|
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
+ ENETDMAC_IR_REG(priv->rx_chan));
|
|
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
+ ENETDMAC_IR_REG(priv->tx_chan));
|
|
+ } else {
|
|
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
|
+ ENETDMA_IR_PKTDONE_MASK |
|
|
+ ENETDMA_IR_NOTOWNER_MASK,
|
|
+ ENETDMA_6345_IR_REG(priv->rx_chan));
|
|
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
|
+ ENETDMA_IR_PKTDONE_MASK |
|
|
+ ENETDMA_IR_NOTOWNER_MASK,
|
|
+ ENETDMA_6345_IR_REG(priv->tx_chan));
|
|
+ }
|
|
|
|
/* make sure we enable napi before rx interrupt */
|
|
napi_enable(&priv->napi);
|
|
|
|
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
- ENETDMAC_IRMASK_REG(priv->rx_chan));
|
|
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
- ENETDMAC_IRMASK_REG(priv->tx_chan));
|
|
+ if (!BCMCPU_IS_6345()) {
|
|
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
+ ENETDMAC_IRMASK_REG(priv->rx_chan));
|
|
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
|
|
+ ENETDMAC_IRMASK_REG(priv->tx_chan));
|
|
+ } else {
|
|
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
|
+ ENETDMA_IR_PKTDONE_MASK |
|
|
+ ENETDMA_IR_NOTOWNER_MASK,
|
|
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
|
|
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
|
+ ENETDMA_IR_PKTDONE_MASK |
|
|
+ ENETDMA_IR_NOTOWNER_MASK,
|
|
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
|
|
+ }
|
|
|
|
if (priv->has_phy)
|
|
phy_start(priv->phydev);
|
|
@@ -1111,13 +1226,19 @@ static void bcm_enet_disable_dma(struct
|
|
{
|
|
int limit;
|
|
|
|
- enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
|
|
+ if (!BCMCPU_IS_6345())
|
|
+ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
|
|
+ else
|
|
+ enet_dma_writel(priv, 0, ENETDMA_6345_CHANCFG_REG(chan));
|
|
|
|
limit = 1000;
|
|
do {
|
|
u32 val;
|
|
|
|
- val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
|
|
+ if (!BCMCPU_IS_6345())
|
|
+ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
|
|
+ else
|
|
+ val = enet_dma_readl(priv, ENETDMA_6345_CHANCFG_REG(chan));
|
|
if (!(val & ENETDMAC_CHANCFG_EN_MASK))
|
|
break;
|
|
udelay(1);
|
|
@@ -1144,8 +1265,13 @@ static int bcm_enet_stop(struct net_devi
|
|
|
|
/* mask all interrupts */
|
|
enet_writel(priv, 0, ENET_IRMASK_REG);
|
|
- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
|
|
- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
|
|
+ if (!BCMCPU_IS_6345()) {
|
|
+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
|
|
+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
|
|
+ } else {
|
|
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
|
|
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
|
|
+ }
|
|
|
|
/* make sure no mib update is scheduled */
|
|
cancel_work_sync(&priv->mib_update_task);
|
|
@@ -1680,6 +1806,7 @@ static int __devinit bcm_enet_probe(stru
|
|
struct mii_bus *bus;
|
|
const char *clk_name;
|
|
int i, ret;
|
|
+ unsigned int chan_offset = 0;
|
|
|
|
/* stop if shared driver failed, assume driver->probe will be
|
|
* called in the same order we register devices (correct ?) */
|
|
@@ -1722,10 +1849,13 @@ static int __devinit bcm_enet_probe(stru
|
|
priv->irq_tx = res_irq_tx->start;
|
|
priv->mac_id = pdev->id;
|
|
|
|
+ if (BCMCPU_IS_6345())
|
|
+ chan_offset = 1;
|
|
+
|
|
/* get rx & tx dma channel id for this mac */
|
|
if (priv->mac_id == 0) {
|
|
- priv->rx_chan = 0;
|
|
- priv->tx_chan = 1;
|
|
+ priv->rx_chan = 0 + chan_offset;
|
|
+ priv->tx_chan = 1 + chan_offset;
|
|
clk_name = "enet0";
|
|
} else {
|
|
priv->rx_chan = 2;
|
|
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
|
|
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
|
|
@@ -47,6 +47,9 @@ struct bcm_enet_desc {
|
|
#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
|
|
#define DMADESC_WRAP_MASK (1 << 12)
|
|
|
|
+/* Shift down for EOP, SOP and WRAP bits */
|
|
+#define DMADESC_6345_SHIFT (3)
|
|
+
|
|
#define DMADESC_UNDER_MASK (1 << 9)
|
|
#define DMADESC_APPEND_CRC (1 << 8)
|
|
#define DMADESC_OVSIZE_MASK (1 << 4)
|