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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31060 3c298f89-4303-0410-b956-a3cf2f4a3e73
125 lines
3.4 KiB
Diff
125 lines
3.4 KiB
Diff
From 58d1ae79d144e6725a68fab99ef6a9b20b25a765 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 21 Feb 2012 21:09:01 +0100
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Subject: [PATCH 37/70] MIPS: lantiq: add ipi handlers to make vsmp work
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Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
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on lantiq SoCs.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/lantiq/irq.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++
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arch/mips/lantiq/prom.c | 5 ++++
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2 files changed, 66 insertions(+), 0 deletions(-)
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diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
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index 0b2ed87..770a10c 100644
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -9,6 +9,7 @@
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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+#include <linux/sched.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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@@ -54,6 +55,14 @@
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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+/* our 2 ipi interrupts for VSMP */
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+#define MIPS_CPU_IPI_RESCHED_IRQ 0
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+#define MIPS_CPU_IPI_CALL_IRQ 1
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+
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+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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+int gic_present;
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+#endif
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+
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static unsigned short ltq_eiu_irq[MAX_EIU] = {
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LTQ_EIU_IR0,
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LTQ_EIU_IR1,
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@@ -219,6 +228,47 @@ static void ltq_hw5_irqdispatch(void)
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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}
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+#ifdef CONFIG_MIPS_MT_SMP
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+void __init arch_init_ipiirq(int irq, struct irqaction *action)
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+{
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+ setup_irq(irq, action);
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+ irq_set_handler(irq, handle_percpu_irq);
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+}
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+
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+static void ltq_sw0_irqdispatch(void)
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+{
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+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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+}
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+
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+static void ltq_sw1_irqdispatch(void)
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+{
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+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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+}
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+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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+{
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+ scheduler_ipi();
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+ return IRQ_HANDLED;
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+}
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+
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+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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+{
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+ smp_call_function_interrupt();
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction irq_resched = {
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+ .handler = ipi_resched_interrupt,
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+ .flags = IRQF_PERCPU,
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+ .name = "IPI_resched"
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+};
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+
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+static struct irqaction irq_call = {
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+ .handler = ipi_call_interrupt,
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+ .flags = IRQF_PERCPU,
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+ .name = "IPI_call"
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+};
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+#endif
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+
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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@@ -314,6 +364,17 @@ void __init arch_init_irq(void)
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irq_set_chip_and_handler(i, <q_irq_type,
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handle_level_irq);
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ if (cpu_has_vint) {
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+ pr_info("Setting up IPI vectored interrupts\n");
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+ set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
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+ set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
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+ }
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+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
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+ &irq_resched);
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+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
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+#endif
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+
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#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
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index 971554b..00ad59c 100644
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--- a/arch/mips/lantiq/prom.c
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+++ b/arch/mips/lantiq/prom.c
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@@ -108,4 +108,9 @@ void __init prom_init(void)
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soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
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pr_info("SoC: %s\n", soc_info.sys_type);
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prom_init_cmdline();
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ if (register_vsmp_smp_ops())
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+ panic("failed to register_vsmp_smp_ops()");
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+#endif
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}
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--
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1.7.7.1
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