mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 13:11:53 +02:00
d02eb8cdaa
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32455 3c298f89-4303-0410-b956-a3cf2f4a3e73
406 lines
10 KiB
C
406 lines
10 KiB
C
/*
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* MikroTik RouterBOARD 4xx series support
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*
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* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/mdio-gpio.h>
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#include <linux/mmc/host.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/spi/mmc_spi.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/rb4xx_cpld.h>
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#include "common.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-usb.h"
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#include "machtypes.h"
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#include "pci.h"
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#define RB4XX_GPIO_USER_LED 4
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#define RB4XX_GPIO_RESET_SWITCH 7
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#define RB4XX_GPIO_CPLD_BASE 32
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#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
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#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
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#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
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#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
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#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
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#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
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#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
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static struct gpio_led rb4xx_leds_gpio[] __initdata = {
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{
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.name = "rb4xx:yellow:user",
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.gpio = RB4XX_GPIO_USER_LED,
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.active_low = 0,
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}, {
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.name = "rb4xx:green:led1",
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.gpio = RB4XX_GPIO_CPLD_LED1,
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.active_low = 1,
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}, {
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.name = "rb4xx:green:led2",
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.gpio = RB4XX_GPIO_CPLD_LED2,
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.active_low = 1,
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}, {
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.name = "rb4xx:green:led3",
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.gpio = RB4XX_GPIO_CPLD_LED3,
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.active_low = 1,
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}, {
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.name = "rb4xx:green:led4",
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.gpio = RB4XX_GPIO_CPLD_LED4,
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.active_low = 1,
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}, {
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.name = "rb4xx:green:led5",
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.gpio = RB4XX_GPIO_CPLD_LED5,
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.active_low = 0,
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},
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};
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static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
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{
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.desc = "reset_switch",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
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.gpio = RB4XX_GPIO_RESET_SWITCH,
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.active_low = 1,
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}
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};
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static struct platform_device rb4xx_nand_device = {
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.name = "rb4xx-nand",
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.id = -1,
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};
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static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
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{
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.slot = 17,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(2),
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}, {
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.slot = 18,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(0),
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}, {
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.slot = 18,
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.pin = 2,
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.irq = ATH79_PCI_IRQ(1),
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}, {
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.slot = 19,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(1),
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}, {
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.slot = 19,
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.pin = 1,
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.irq = ATH79_PCI_IRQ(2),
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}
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};
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static struct mtd_partition rb4xx_partitions[] = {
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{
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.name = "routerboot",
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.offset = 0,
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.size = 0x0b000,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "hard_config",
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.offset = 0x0b000,
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.size = 0x01000,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "bios",
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.offset = 0x0d000,
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.size = 0x02000,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "soft_config",
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.offset = 0x0f000,
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.size = 0x01000,
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}
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};
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static struct flash_platform_data rb4xx_flash_data = {
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.type = "pm25lv512",
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.parts = rb4xx_partitions,
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.nr_parts = ARRAY_SIZE(rb4xx_partitions),
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};
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static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
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.gpio_base = RB4XX_GPIO_CPLD_BASE,
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};
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static struct mmc_spi_platform_data rb4xx_mmc_data = {
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.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
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};
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static struct spi_board_info rb4xx_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p80",
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.platform_data = &rb4xx_flash_data,
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}, {
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.bus_num = 0,
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.chip_select = 1,
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.max_speed_hz = 25000000,
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.modalias = "spi-rb4xx-cpld",
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.platform_data = &rb4xx_cpld_data,
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}
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};
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static struct spi_board_info rb4xx_microsd_info[] = {
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{
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.bus_num = 0,
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.chip_select = 2,
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.max_speed_hz = 25000000,
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.modalias = "mmc_spi",
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.platform_data = &rb4xx_mmc_data,
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}
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};
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static struct resource rb4xx_spi_resources[] = {
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{
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.start = AR71XX_SPI_BASE,
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.end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device rb4xx_spi_device = {
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.name = "rb4xx-spi",
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.id = -1,
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.resource = rb4xx_spi_resources,
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.num_resources = ARRAY_SIZE(rb4xx_spi_resources),
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};
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static void __init rb4xx_generic_setup(void)
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{
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ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
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AR71XX_GPIO_FUNC_SPI_CS2_EN);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
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rb4xx_leds_gpio);
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ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(rb4xx_gpio_keys),
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rb4xx_gpio_keys);
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spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
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platform_device_register(&rb4xx_spi_device);
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platform_device_register(&rb4xx_nand_device);
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}
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static void __init rb411_setup(void)
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{
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rb4xx_generic_setup();
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spi_register_board_info(rb4xx_microsd_info,
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ARRAY_SIZE(rb4xx_microsd_info));
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ath79_register_mdio(0, 0xfffffffc);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = 0x00000003;
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ath79_register_eth(0);
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ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
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rb411_setup);
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static void __init rb411u_setup(void)
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{
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rb411_setup();
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ath79_register_usb();
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}
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MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
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rb411u_setup);
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#define RB433_LAN_PHYMASK BIT(0)
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#define RB433_WAN_PHYMASK BIT(4)
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#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
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static void __init rb433_setup(void)
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{
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rb4xx_generic_setup();
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spi_register_board_info(rb4xx_microsd_info,
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ARRAY_SIZE(rb4xx_microsd_info));
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ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
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ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
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ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
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ath79_register_eth(1);
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ath79_register_eth(0);
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ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
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rb433_setup);
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static void __init rb433u_setup(void)
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{
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rb433_setup();
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ath79_register_usb();
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}
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MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
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rb433u_setup);
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#define RB450_LAN_PHYMASK BIT(0)
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#define RB450_WAN_PHYMASK BIT(4)
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#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
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static void __init rb450_generic_setup(int gige)
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{
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rb4xx_generic_setup();
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ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
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ath79_eth0_data.phy_if_mode = (gige) ?
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PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
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ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
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ath79_eth1_data.phy_if_mode = (gige) ?
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PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
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ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
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ath79_register_eth(1);
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ath79_register_eth(0);
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}
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static void __init rb450_setup(void)
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{
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rb450_generic_setup(0);
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}
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MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
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rb450_setup);
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static void __init rb450g_setup(void)
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{
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rb450_generic_setup(1);
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spi_register_board_info(rb4xx_microsd_info,
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ARRAY_SIZE(rb4xx_microsd_info));
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}
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MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
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rb450g_setup);
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static void __init rb493_setup(void)
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{
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rb4xx_generic_setup();
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ath79_register_mdio(0, 0x3fffff00);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.speed = SPEED_100;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
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ath79_eth1_data.phy_mask = 0x00000001;
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ath79_register_eth(0);
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ath79_register_eth(1);
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ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
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rb493_setup);
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#define RB493G_GPIO_MDIO_MDC 7
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#define RB493G_GPIO_MDIO_DATA 8
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#define RB493G_MDIO_PHYMASK BIT(0)
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static struct mdio_gpio_platform_data rb493g_mdio_data = {
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.mdc = RB493G_GPIO_MDIO_MDC,
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.mdio = RB493G_GPIO_MDIO_DATA,
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.phy_mask = ~RB493G_MDIO_PHYMASK,
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};
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static struct platform_device rb493g_mdio_device = {
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.name = "mdio-gpio",
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.id = -1,
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.dev = {
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.platform_data = &rb493g_mdio_data,
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},
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};
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static void __init rb493g_setup(void)
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{
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ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
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AR71XX_GPIO_FUNC_SPI_CS2_EN);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
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rb4xx_leds_gpio);
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spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
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platform_device_register(&rb4xx_spi_device);
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platform_device_register(&rb4xx_nand_device);
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ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
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ath79_eth0_data.speed = SPEED_1000;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
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ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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platform_device_register(&rb493g_mdio_device);
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ath79_register_eth(1);
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ath79_register_eth(0);
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ath79_register_usb();
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ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
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rb493g_setup);
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