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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
122 lines
4.1 KiB
Diff
122 lines
4.1 KiB
Diff
From 5c56f76995691cf761f66d6d89a00eea80be660c Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 20 Jul 2012 19:01:00 +0200
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Subject: [PATCH 12/15] Document: devicetree: add OF documents for lantiq xway
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pinctrl
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Cc: devicetree-discuss@lists.ozlabs.org
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Cc: linux-kernel@vger.kernel.org
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---
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.../bindings/pinctrl/lantiq,xway-pinumx.txt | 97 ++++++++++++++++++++
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1 file changed, 97 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
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diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
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new file mode 100644
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index 0000000..b5469db
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
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@@ -0,0 +1,97 @@
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+Lantiq XWAY pinmux controller
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+
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+Required properties:
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+- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
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+- reg: Should contain the physical address and length of the gpio/pinmux
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+ register range
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+
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+Please refer to pinctrl-bindings.txt in this directory for details of the
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+common pinctrl bindings used by client devices, including the meaning of the
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+phrase "pin configuration node".
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+
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+Lantiq's pin configuration nodes act as a container for an abitrary number of
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+subnodes. Each of these subnodes represents some desired configuration for a
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+pin, a group, or a list of pins or groups. This configuration can include the
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+mux function to select on those group(s), and two pin configuration parameters:
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+pull-up and open-drain
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+
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+The name of each subnode is not important as long as it is unique; all subnodes
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+should be enumerated and processed purely based on their content.
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+
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+Each subnode only affects those parameters that are explicitly listed. In
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+other words, a subnode that lists a mux function but no pin configuration
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+parameters implies no information about any pin configuration parameters.
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+Similarly, a pin subnode that describes a pullup parameter implies no
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+information about e.g. the mux function.
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+
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+We support 2 types of nodes.
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+
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+Definition of mux function groups:
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+
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+Required subnode-properties:
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+- lantiq,groups : An array of strings. Each string contains the name of a group.
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+ Valid values for these names are listed below.
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+- lantiq,function: A string containing the name of the function to mux to the
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+ group. Valid values for function names are listed below.
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+
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+Valid values for group and function names:
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+
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+ mux groups:
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+ exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
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+ ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
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+ spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
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+ gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
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+ req3
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+
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+ additional mux groups (XR9 only):
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+ mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
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+
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+ functions:
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+ spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
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+
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+
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+
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+Definition of pin configurations:
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+
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+Required subnode-properties:
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+- lantiq,pins : An array of strings. Each string contains the name of a pin.
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+ Valid values for these names are listed below.
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+
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+Optional subnode-properties:
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+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
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+ 0: none, 1: down, 2: up.
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+- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
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+
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+Valid values for XWAY pin names:
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+ Pinconf pins can be referenced via the names io0-io31.
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+
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+Valid values for XR9 pin names:
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+ Pinconf pins can be referenced via the names io0-io55.
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+
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+Example:
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+ gpio: pinmux@E100B10 {
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+ compatible = "lantiq,pinctrl-xway";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&state_default>;
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+
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+ #gpio-cells = <2>;
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+ gpio-controller;
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+ reg = <0xE100B10 0xA0>;
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+
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+ state_default: pinmux {
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+ stp {
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+ lantiq,groups = "stp";
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+ lantiq,function = "stp";
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+ };
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+ pci {
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+ lantiq,groups = "gnt1";
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+ lantiq,function = "pci";
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+ };
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+ conf_out {
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+ lantiq,pins = "io4", "io5", "io6"; /* stp */
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+ lantiq,open-drain;
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+ lantiq,pull = <0>;
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+ };
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+ };
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+ };
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+
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--
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1.7.10.4
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