mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-01 20:33:08 +02:00
6ddec82f97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11596 3c298f89-4303-0410-b956-a3cf2f4a3e73
432 lines
11 KiB
C
432 lines
11 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2007 Xu Liang, infineon
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* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <asm/unistd.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <linux/errno.h>
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#include <asm/ifxmips/ifxmips.h>
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#define FIX_FOR_36M_CRYSTAL 1
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#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
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#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
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#define BASIS_INPUT_CRYSTAL_USB 12000000
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#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
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#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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#define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
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#define CGU_PLL0_BYPASS (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
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#define CGU_PLL0_SRC (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
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#define CGU_PLL0_CFG_DSMSEL (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
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#define CGU_PLL0_CFG_FRAC_EN (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
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#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
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#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
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#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
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#define CGU_PLL1_SRC (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
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#define CGU_PLL1_BYPASS (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
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#define CGU_PLL1_CFG_DSMSEL (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
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#define CGU_PLL1_CFG_FRAC_EN (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
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#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
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#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
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#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
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#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
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#define CGU_PLL2_BYPASS (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
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#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
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#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
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#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
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#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
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#define CGU_SYS_PPESEL GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
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#define CGU_SYS_FPI_SEL (*IFXMIPS_CGU_SYS & (1 << 6))
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#define CGU_SYS_CPU1SEL GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
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#define CGU_SYS_CPU0SEL GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
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#define CGU_SYS_DDR_SEL GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
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#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
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#define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
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#define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
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static unsigned int cgu_get_pll0_fdiv(void);
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static inline unsigned int
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get_input_clock(int pll)
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{
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switch(pll)
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{
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case 0:
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if(CGU_PLL0_SRC)
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return BASIS_INPUT_CRYSTAL_USB;
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else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
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return BASIC_INPUT_CLOCK_FREQUENCY_1;
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else
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return BASIC_INPUT_CLOCK_FREQUENCY_2;
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case 1:
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if(CGU_PLL1_SRC)
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return BASIS_INPUT_CRYSTAL_USB;
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else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
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return BASIC_INPUT_CLOCK_FREQUENCY_1;
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else
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return BASIC_INPUT_CLOCK_FREQUENCY_2;
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case 2:
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switch(CGU_PLL2_SRC)
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{
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case 0:
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return cgu_get_pll0_fdiv();
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case 1:
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return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
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case 2:
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return BASIS_INPUT_CRYSTAL_USB;
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}
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default:
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return 0;
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}
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}
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static inline unsigned int
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cal_dsm(int pll, unsigned int num, unsigned int den)
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{
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u64 res, clock = get_input_clock(pll);
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res = num * clock;
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do_div(res, den);
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return res;
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}
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static inline unsigned int
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mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
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{
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unsigned int num = ((N + 1) << 10) + K;
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unsigned int den = (M + 1) << 10;
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return cal_dsm(pll, num, den);
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}
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static inline unsigned int
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ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
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{
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unsigned int num = ((N + 1) << 11) + K + 512;
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unsigned int den = (M + 1) << 11;
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return cal_dsm(pll, num, den);
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}
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static inline unsigned int
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ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
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{
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unsigned int num = K >= 512 ?
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((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
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unsigned int den = (M + 1) << 12;
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return cal_dsm(pll, num, den);
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}
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static inline unsigned int
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dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
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unsigned int dsmsel, unsigned int phase_div_en)
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{
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if(!dsmsel)
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return mash_dsm(pll, M, N, K);
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else if(!phase_div_en)
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return mash_dsm(pll, M, N, K);
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else
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return ssff_dsm_2(pll, M, N, K);
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}
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static inline unsigned int
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cgu_get_pll0_fosc(void)
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{
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if(CGU_PLL0_BYPASS)
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return get_input_clock(0);
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else
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return !CGU_PLL0_CFG_FRAC_EN
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? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
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CGU_PLL0_PHASE_DIVIDER_ENABLE)
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: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
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CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
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}
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static inline unsigned int
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cgu_get_pll0_fps(int phase)
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{
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register unsigned int fps = cgu_get_pll0_fosc();
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switch(phase)
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{
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case 1:
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/* 1.25 */
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fps = ((fps << 2) + 2) / 5;
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break;
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case 2:
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/* 1.5 */
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fps = ((fps << 1) + 1) / 3;
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break;
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}
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return fps;
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}
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static unsigned int
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cgu_get_pll0_fdiv(void)
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{
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register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
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return (cgu_get_pll0_fosc() + (div >> 1)) / div;
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}
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static inline unsigned int
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cgu_get_pll1_fosc(void)
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{
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if(CGU_PLL1_BYPASS)
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return get_input_clock(1);
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else
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return !CGU_PLL1_CFG_FRAC_EN
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? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
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: dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
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}
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static inline unsigned int
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cgu_get_pll1_fps(void)
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{
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register unsigned int fps = cgu_get_pll1_fosc();
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return ((fps << 1) + 1) / 3;
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}
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static inline unsigned int
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cgu_get_pll1_fdiv(void)
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{
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return cgu_get_pll1_fosc();
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}
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static inline unsigned int
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cgu_get_pll2_fosc(void)
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{
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u64 res, clock = get_input_clock(2);
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if ( CGU_PLL2_BYPASS )
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return get_input_clock(2);
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res = (CGU_PLL2_CFG_PLLN + 1) * clock;
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do_div(res, CGU_PLL2_CFG_PLLM + 1);
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return res;
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}
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static inline unsigned int
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cgu_get_pll2_fps(int phase)
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{
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register unsigned int fps = cgu_get_pll2_fosc();
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switch ( phase )
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{
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case 1:
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/* 1.125 */
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fps = ((fps << 2) + 2) / 5; break;
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case 2:
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/* 1.25 */
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fps = ((fps << 3) + 4) / 9;
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}
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return fps;
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}
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static inline unsigned int
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cgu_get_pll2_fdiv(void)
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{
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register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
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return (cgu_get_pll2_fosc() + (div >> 1)) / div;
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}
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unsigned int
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cgu_get_mips_clock(int cpu)
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{
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register unsigned int ret = cgu_get_pll0_fosc();
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register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
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if(cpusel == 0)
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return ret;
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else if(cpusel == 2)
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ret <<= 1;
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switch(CGU_SYS_DDR_SEL)
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{
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default:
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case 0:
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return (ret + 1) / 2;
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case 1:
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return (ret * 2 + 2) / 5;
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case 2:
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return (ret + 1) / 3;
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case 3:
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return (ret + 2) / 4;
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}
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}
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unsigned int
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cgu_get_cpu_clock(void)
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{
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return cgu_get_mips_clock(0);
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}
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unsigned int
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cgu_get_io_region_clock(void)
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{
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register unsigned int ret = cgu_get_pll0_fosc();
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switch(CGU_SYS_DDR_SEL)
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{
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default:
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case 0:
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return (ret + 1) / 2;
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case 1:
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return (ret * 2 + 2) / 5;
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case 2:
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return (ret + 1) / 3;
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case 3:
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return (ret + 2) / 4;
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}
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}
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unsigned int
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cgu_get_fpi_bus_clock(int fpi)
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{
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register unsigned int ret = cgu_get_io_region_clock();
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if((fpi == 2) && (CGU_SYS_FPI_SEL))
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ret >>= 1;
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return ret;
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}
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unsigned int
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cgu_get_pp32_clock(void)
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{
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switch(CGU_SYS_PPESEL)
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{
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default:
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case 0:
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return cgu_get_pll2_fps(1);
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case 1:
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return cgu_get_pll2_fps(2);
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case 2:
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return (cgu_get_pll2_fps(1) + 1) >> 1;
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case 3:
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return (cgu_get_pll2_fps(2) + 1) >> 1;
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}
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}
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unsigned int
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cgu_get_ethernet_clock(int mii)
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{
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switch(CGU_IF_CLK_MIISEL)
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{
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case 0:
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return (cgu_get_pll2_fosc() + 3) / 12;
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case 1:
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return (cgu_get_pll2_fosc() + 3) / 6;
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case 2:
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return 50000000;
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case 3:
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return 25000000;
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}
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return 0;
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}
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unsigned int
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cgu_get_usb_clock(void)
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{
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switch(CGU_IF_CLK_USBSEL)
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{
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case 0:
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return (cgu_get_pll2_fosc() + 12) / 25;
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case 1:
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return 12000000;
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case 2:
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return 12000000 / 4;
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case 3:
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return 12000000;
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}
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return 0;
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}
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unsigned int
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cgu_get_clockout(int clkout)
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{
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unsigned int fosc1 = cgu_get_pll1_fosc();
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unsigned int fosc2 = cgu_get_pll2_fosc();
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if(clkout > 3 || clkout < 0)
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return 0;
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switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
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{
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case 0: /* 32.768KHz */
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case 15:
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return (fosc1 + 6000) / 12000;
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case 1: /* 1.536MHz */
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return (fosc1 + 128) / 256;
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case 2: /* 2.5MHz */
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return (fosc2 + 60) / 120;
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case 3: /* 12MHz */
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case 5:
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case 12:
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return (fosc2 + 12) / 25;
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case 4: /* 40MHz */
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return (cgu_get_pll2_fps(2) + 3) / 6;
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case 6: /* 24MHz */
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return (cgu_get_pll2_fps(2) + 5) / 10;
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case 7: /* 48MHz */
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return (cgu_get_pll2_fps(2) + 2) / 5;
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case 8: /* 25MHz */
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case 14:
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return (fosc2 + 6) / 12;
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case 9: /* 50MHz */
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case 13:
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return (fosc2 + 3) / 6;
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case 10:/* 30MHz */
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return (fosc2 + 5) / 10;
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case 11:/* 60MHz */
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return (fosc2 + 2) / 5;
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}
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return 0;
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}
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void cgu_setup_pci_clk(int external_clock)
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{
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//set clock to 33Mhz
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
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// internal or external clock
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if(external_clock)
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{
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
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ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
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} else {
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
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ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
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}
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}
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