nbd 6e65867e28 cns3xxx: Fix laguna arm11mpcore watchdog ... The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where all mpcore-wdt boards point the driver base too. I believe this is wrong because 0x600 is aliased to the timer/watchdog of the 'current CPU' where 0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus if your timer/watchdog application is switching between CPU's it can end up writing to the wrong CPU's registers which results in random board resets from watchdog timeouts etc. This patch forces the timer/watchdog driver to use CPU0's registers always. Its my opinion that other mpcore-wdt boards should be doing the same thing. Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33683 3c298f89-4303-0410-b956-a3cf2f4a3e73		2012-10-10 11:38:58 +00:00
..
base-files/lib	cns3xxx: add sysupgrade support	2012-10-07 23:24:02 +00:00
image	cns3xxx: add sysupgrade support	2012-10-07 23:24:02 +00:00
patches-3.3	cns3xxx: Fix laguna arm11mpcore watchdog	2012-10-10 11:38:58 +00:00
config-3.3	cns3xxx: add missing kernel config symbol	2012-09-30 15:31:34 +00:00
Makefile	cns3xxx: remove the broken flag	2012-09-19 23:50:25 +00:00