mirror of
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b1704a799d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20288 3c298f89-4303-0410-b956-a3cf2f4a3e73
410 lines
9.8 KiB
C
410 lines
9.8 KiB
C
/*
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* Atheros AR71xx PCI host controller driver
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/resource.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/interrupt.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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#define AR71XX_PCI_DELAY 100 /* msecs */
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#if 0
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#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
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#else
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#define PCI_IDSEL_BASE 0
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#endif
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static void __iomem *ar71xx_pcicfg_base;
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static DEFINE_SPINLOCK(ar71xx_pci_lock);
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static int ar71xx_pci_fixup_enable;
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static inline void ar71xx_pci_delay(void)
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{
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mdelay(AR71XX_PCI_DELAY);
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}
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/* Byte lane enable bits */
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static u8 ble_table[4][4] = {
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{0x0, 0xf, 0xf, 0xf},
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{0xe, 0xd, 0xb, 0x7},
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{0xc, 0xf, 0x3, 0xf},
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{0xf, 0xf, 0xf, 0xf},
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};
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static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
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{
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u32 t;
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t = ble_table[size & 3][where & 3];
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BUG_ON(t == 0xf);
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t <<= (local) ? 20 : 4;
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return t;
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}
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static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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u32 ret;
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if (!bus->number) {
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/* type 0 */
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ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
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| (PCI_FUNC(devfn) << 8) | (where & ~3);
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} else {
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/* type 1 */
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ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
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| (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
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}
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return ret;
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}
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int ar71xx_pci_be_handler(int is_fixup)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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u32 pci_err;
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u32 ahb_err;
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pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;
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if (pci_err) {
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if (!is_fixup)
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printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
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pci_err,
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__raw_readl(base + PCI_REG_PCI_ERR_ADDR));
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__raw_writel(pci_err, base + PCI_REG_PCI_ERR);
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}
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ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;
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if (ahb_err) {
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if (!is_fixup)
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printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
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__raw_readl(base + PCI_REG_AHB_ERR_ADDR));
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__raw_writel(ahb_err, base + PCI_REG_AHB_ERR);
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}
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return ((ahb_err | pci_err) ? 1 : 0);
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}
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static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 cmd)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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u32 addr;
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addr = ar71xx_pci_bus_addr(bus, devfn, where);
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DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, addr);
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__raw_writel(addr, base + PCI_REG_CFG_AD);
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__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
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base + PCI_REG_CFG_CBE);
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return ar71xx_pci_be_handler(1);
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}
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static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
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unsigned long flags;
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u32 data;
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int ret;
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ret = PCIBIOS_SUCCESSFUL;
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DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
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spin_lock_irqsave(&ar71xx_pci_lock, flags);
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if (bus->number == 0 && devfn == 0) {
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u32 t;
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t = PCI_CRP_CMD_READ | (where & ~3);
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__raw_writel(t, base + PCI_REG_CRP_AD_CBE);
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data = __raw_readl(base + PCI_REG_CRP_RDDATA);
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DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
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} else {
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int err;
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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PCI_CFG_CMD_READ);
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if (err == 0) {
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data = __raw_readl(base + PCI_REG_CFG_RDDATA);
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} else {
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ret = PCIBIOS_DEVICE_NOT_FOUND;
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data = ~0;
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}
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}
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spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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DBG("PCI: read config: data=%08x raw=%08x\n",
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(data >> (8 * (where & 3))) & mask[size & 7], data);
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*value = (data >> (8 * (where & 3))) & mask[size & 7];
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return ret;
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}
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static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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unsigned long flags;
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int ret;
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DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, value);
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value = value << (8 * (where & 3));
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ret = PCIBIOS_SUCCESSFUL;
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spin_lock_irqsave(&ar71xx_pci_lock, flags);
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if (bus->number == 0 && devfn == 0) {
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u32 t;
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t = PCI_CRP_CMD_WRITE | (where & ~3);
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t |= ar71xx_pci_get_ble(where, size, 1);
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DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
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__raw_writel(t, base + PCI_REG_CRP_AD_CBE);
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__raw_writel(value, base + PCI_REG_CRP_WRDATA);
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} else {
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int err;
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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PCI_CFG_CMD_WRITE);
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if (err == 0)
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__raw_writel(value, base + PCI_REG_CFG_WRDATA);
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else
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ret = PCIBIOS_DEVICE_NOT_FOUND;
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}
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spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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return ret;
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}
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static void ar71xx_pci_fixup(struct pci_dev *dev)
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{
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u32 t;
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if (!ar71xx_pci_fixup_enable)
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return;
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if (dev->bus->number != 0 || dev->devfn != 0)
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return;
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DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
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dev->vendor, dev->device);
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/* setup COMMAND register */
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
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| PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
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pci_write_config_word(dev, PCI_COMMAND, t);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
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int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
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uint8_t pin)
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{
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int irq = -1;
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int i;
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slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
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for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
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struct ar71xx_pci_irq *entry;
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entry = &ar71xx_pci_irq_map[i];
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if (entry->slot == slot && entry->pin == pin) {
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irq = entry->irq;
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break;
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}
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}
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if (irq < 0) {
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printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
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pin, pci_name((struct pci_dev *)dev));
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} else {
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printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
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irq, pin, pci_name((struct pci_dev *)dev));
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}
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return irq;
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}
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static struct pci_ops ar71xx_pci_ops = {
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.read = ar71xx_pci_read_config,
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.write = ar71xx_pci_write_config,
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};
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static struct resource ar71xx_pci_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ar71xx_pci_mem_resource = {
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.name = "PCI memory space",
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.start = AR71XX_PCI_MEM_BASE,
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.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ar71xx_pci_controller = {
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.pci_ops = &ar71xx_pci_ops,
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.mem_resource = &ar71xx_pci_mem_resource,
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.io_resource = &ar71xx_pci_io_resource,
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};
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static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ar71xx_reset_base;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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if (pending & PCI_INT_DEV0)
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generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
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else if (pending & PCI_INT_DEV1)
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generic_handle_irq(AR71XX_PCI_IRQ_DEV1);
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else if (pending & PCI_INT_DEV2)
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generic_handle_irq(AR71XX_PCI_IRQ_DEV2);
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else if (pending & PCI_INT_CORE)
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generic_handle_irq(AR71XX_PCI_IRQ_CORE);
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else
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spurious_interrupt();
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}
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static void ar71xx_pci_irq_unmask(unsigned int irq)
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{
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void __iomem *base = ar71xx_reset_base;
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u32 t;
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irq -= AR71XX_PCI_IRQ_BASE;
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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}
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static void ar71xx_pci_irq_mask(unsigned int irq)
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{
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void __iomem *base = ar71xx_reset_base;
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u32 t;
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irq -= AR71XX_PCI_IRQ_BASE;
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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/* flush write */
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(void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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}
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static struct irq_chip ar71xx_pci_irq_chip = {
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.name = "AR71XX PCI ",
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.mask = ar71xx_pci_irq_mask,
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.unmask = ar71xx_pci_irq_unmask,
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.mask_ack = ar71xx_pci_irq_mask,
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};
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static void __init ar71xx_pci_irq_init(void)
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{
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void __iomem *base = ar71xx_reset_base;
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int i;
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__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
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for (i = AR71XX_PCI_IRQ_BASE;
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
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handle_level_irq);
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}
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set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
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}
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int __init ar71xx_pcibios_init(void)
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{
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void __iomem *ddr_base = ar71xx_ddr_base;
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ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
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ar71xx_pci_delay();
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ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
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ar71xx_pci_delay();
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ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
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AR71XX_PCI_CFG_SIZE);
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if (ar71xx_pcicfg_base == NULL)
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return -ENOMEM;
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__raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
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__raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
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__raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
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__raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
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__raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
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__raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
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__raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
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__raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
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ar71xx_pci_delay();
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/* clear bus errors */
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(void)ar71xx_pci_be_handler(1);
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ar71xx_pci_fixup_enable = 1;
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ar71xx_pci_irq_init();
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register_pci_controller(&ar71xx_pci_controller);
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return 0;
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}
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