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git://projects.qi-hardware.com/openwrt-xburst.git
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6e809dd8f1
This also adds minimal support for the BCMA43224 pcie wireless card. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29843 3c298f89-4303-0410-b956-a3cf2f4a3e73
335 lines
14 KiB
Diff
335 lines
14 KiB
Diff
From 300efafa8e1381a208c723bb9d03d46bf29f1ec0 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sat, 14 Jan 2012 20:02:15 +0100
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Subject: [PATCH 24/31] bcma: constants for PCI and use them
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There are loots of magic numbers used in the PCIe code. These constants
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are from the Broadcom SDK and will also used in the host controller.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/bcma/driver_pci.c | 124 +++++++++++++++++++---------------
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include/linux/bcma/bcma_driver_pci.h | 85 +++++++++++++++++++++++
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2 files changed, 155 insertions(+), 54 deletions(-)
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--- a/drivers/bcma/driver_pci.c
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+++ b/drivers/bcma/driver_pci.c
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@@ -4,6 +4,7 @@
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@@ -18,38 +19,39 @@
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static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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- pcicore_write32(pc, 0x130, address);
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- pcicore_read32(pc, 0x130);
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- return pcicore_read32(pc, 0x134);
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+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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+ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
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}
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#if 0
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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- pcicore_write32(pc, 0x130, address);
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- pcicore_read32(pc, 0x130);
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- pcicore_write32(pc, 0x134, data);
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+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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#endif
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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{
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- const u16 mdio_control = 0x128;
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- const u16 mdio_data = 0x12C;
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u32 v;
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int i;
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- v = (1 << 30); /* Start of Transaction */
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- v |= (1 << 28); /* Write Transaction */
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- v |= (1 << 17); /* Turnaround */
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- v |= (0x1F << 18);
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+ v = BCMA_CORE_PCI_MDIODATA_START;
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+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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+ v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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+ v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
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+ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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+ v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= (phy << 4);
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- pcicore_write32(pc, mdio_data, v);
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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- v = pcicore_read32(pc, mdio_control);
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- if (v & 0x100 /* Trans complete */)
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+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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msleep(1);
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}
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@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struc
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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{
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- const u16 mdio_control = 0x128;
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- const u16 mdio_data = 0x12C;
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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- v = 0x80; /* Enable Preamble Sequence */
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- v |= 0x2; /* MDIO Clock Divisor */
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- pcicore_write32(pc, mdio_control, v);
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+ /* enable mdio access to SERDES */
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+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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+ } else {
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+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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- v = (1 << 30); /* Start of Transaction */
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- v |= (1 << 29); /* Read Transaction */
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- v |= (1 << 17); /* Turnaround */
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- if (pc->core->id.rev < 10)
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- v |= (u32)device << 22;
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- v |= (u32)address << 18;
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- pcicore_write32(pc, mdio_data, v);
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+ v = BCMA_CORE_PCI_MDIODATA_START;
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+ v |= BCMA_CORE_PCI_MDIODATA_READ;
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+ v |= BCMA_CORE_PCI_MDIODATA_TA;
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+
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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- v = pcicore_read32(pc, mdio_control);
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- if (v & 0x100 /* Trans complete */) {
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+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
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udelay(10);
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- ret = pcicore_read32(pc, mdio_data);
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+ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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}
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msleep(1);
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}
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- pcicore_write32(pc, mdio_control, 0);
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
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u8 address, u16 data)
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{
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- const u16 mdio_control = 0x128;
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- const u16 mdio_data = 0x12C;
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int max_retries = 10;
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u32 v;
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int i;
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- v = 0x80; /* Enable Preamble Sequence */
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- v |= 0x2; /* MDIO Clock Divisor */
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- pcicore_write32(pc, mdio_control, v);
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+ /* enable mdio access to SERDES */
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+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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+ v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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+ } else {
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+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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+ v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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- v = (1 << 30); /* Start of Transaction */
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- v |= (1 << 28); /* Write Transaction */
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- v |= (1 << 17); /* Turnaround */
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- if (pc->core->id.rev < 10)
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- v |= (u32)device << 22;
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- v |= (u32)address << 18;
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+ v = BCMA_CORE_PCI_MDIODATA_START;
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+ v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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+ v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= data;
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- pcicore_write32(pc, mdio_data, v);
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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- v = pcicore_read32(pc, mdio_control);
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- if (v & 0x100 /* Trans complete */)
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+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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msleep(1);
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}
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- pcicore_write32(pc, mdio_control, 0);
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+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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/**************************************************
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@@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct
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static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
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{
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- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
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+ u32 tmp;
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+
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+ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
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+ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
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+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
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+ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
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+ else
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+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
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}
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static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
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{
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- const u8 serdes_pll_device = 0x1D;
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- const u8 serdes_rx_device = 0x1F;
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u16 tmp;
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- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
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- bcma_pcicore_polarity_workaround(pc));
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- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
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- if (tmp & 0x4000)
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- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
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+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
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+ BCMA_CORE_PCI_SERDES_RX_CTRL,
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+ bcma_pcicore_polarity_workaround(pc));
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+ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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+ BCMA_CORE_PCI_SERDES_PLL_CTRL);
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+ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
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+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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+ BCMA_CORE_PCI_SERDES_PLL_CTRL,
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+ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
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}
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/**************************************************
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--- a/include/linux/bcma/bcma_driver_pci.h
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+++ b/include/linux/bcma/bcma_driver_pci.h
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@@ -53,6 +53,35 @@ struct pci_dev;
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#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
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#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
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#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
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+#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
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+#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
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+#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
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+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
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+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
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+#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
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+#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
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+#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
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+#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
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+#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
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+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
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+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
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+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
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+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
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+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
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+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
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+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
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+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
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+#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
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+#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
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+#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
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+#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
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+#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
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+#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
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+#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
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+#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
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+#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
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+#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
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+#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
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#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
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#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
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#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
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@@ -72,6 +101,62 @@ struct pci_dev;
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#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
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#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
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+/* PCIE protocol PHY diagnostic registers */
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+#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
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+#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
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+#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
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+#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
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+#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
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+#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
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+#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
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+#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
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+#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
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+#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
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+#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
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+#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
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+#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
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+#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
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+#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
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+#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
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+#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
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+
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+/* PCIE protocol DLLP diagnostic registers */
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+#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
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+#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
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+#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
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+#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
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+#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
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+#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
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+#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
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+#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
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+#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
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+#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
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+#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
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+#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
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+#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
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+#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
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+#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
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+#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
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+#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
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+#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
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+#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
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+#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
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+#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
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+#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
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+#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
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+
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+/* SERDES RX registers */
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+#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
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+#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
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+#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
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+#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
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+#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
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+#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
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+
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+/* SERDES PLL registers */
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+#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
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+#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
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+
|
|
/* PCIcore specific boardflags */
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|
#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
|
|
|