mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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9e8e8b51d6
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30575 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 lines
4.8 KiB
C
155 lines
4.8 KiB
C
/*
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* Ralink RT3662/RT3883 SoC specific definitions
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_H_
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#define _RT3883_H_
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#include <linux/init.h>
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#include <linux/io.h>
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void rt3883_detect_sys_type(void);
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#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
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#define RT3883_CPU_IRQ_BASE 0
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#define RT3883_CPU_IRQ_COUNT 8
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#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
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#define RT3883_INTC_IRQ_COUNT 32
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#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
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#define RT3883_GPIO_IRQ_COUNT 96
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#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT)
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#define RT3883_PCI_IRQ_COUNT 3
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#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
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#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
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#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
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#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
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#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
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#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
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#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
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#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
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#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
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#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
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#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
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#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
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#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
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#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
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#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
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#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
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#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
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#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
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#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
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#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0)
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#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1)
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#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2)
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extern void __iomem *rt3883_sysc_base;
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extern void __iomem *rt3883_memc_base;
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static inline void rt3883_sysc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt3883_sysc_base + reg);
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}
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static inline u32 rt3883_sysc_rr(unsigned reg)
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{
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return __raw_readl(rt3883_sysc_base + reg);
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}
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static inline void rt3883_memc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt3883_memc_base + reg);
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}
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static inline u32 rt3883_memc_rr(unsigned reg)
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{
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return __raw_readl(rt3883_memc_base + reg);
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}
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#define RT3883_GPIO_I2C_SD 1
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#define RT3883_GPIO_I2C_SCLK 2
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#define RT3883_GPIO_SPI_CS0 3
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#define RT3883_GPIO_SPI_CLK 4
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#define RT3883_GPIO_SPI_MOSI 5
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#define RT3883_GPIO_SPI_MISO 6
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/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
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#define RT3883_GPIO_7 7
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#define RT3883_GPIO_8 8
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#define RT3883_GPIO_9 9
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#define RT3883_GPIO_10 10
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#define RT3883_GPIO_11 11
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#define RT3883_GPIO_12 12
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#define RT3883_GPIO_13 13
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#define RT3883_GPIO_14 14
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#define RT3883_GPIO_UART1_TXD 15
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#define RT3883_GPIO_UART1_RXD 16
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#define RT3883_GPIO_JTAG_TDO 17
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#define RT3883_GPIO_JTAG_TDI 18
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#define RT3883_GPIO_JTAG_TMS 19
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#define RT3883_GPIO_JTAG_TCLK 20
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#define RT3883_GPIO_JTAG_TRST_N 21
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#define RT3883_GPIO_MDIO_MDC 22
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#define RT3883_GPIO_MDIO_MDIO 23
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#define RT3883_GPIO_LNA_PE_A0 32
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#define RT3883_GPIO_LNA_PE_A1 33
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#define RT3883_GPIO_LNA_PE_A2 34
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#define RT3883_GPIO_LNA_PE_G0 35
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#define RT3883_GPIO_LNA_PE_G1 36
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#define RT3883_GPIO_LNA_PE_G2 37
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#define RT3883_GPIO_PCI_AD0 40
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#define RT3883_GPIO_PCI_AD31 71
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#define RT3883_GPIO_GE2_TXD0 72
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#define RT3883_GPIO_GE2_TXD1 73
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#define RT3883_GPIO_GE2_TXD2 74
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#define RT3883_GPIO_GE2_TXD3 75
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#define RT3883_GPIO_GE2_TXEN 76
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#define RT3883_GPIO_GE2_TXCLK 77
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#define RT3883_GPIO_GE2_RXD0 78
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#define RT3883_GPIO_GE2_RXD1 79
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#define RT3883_GPIO_GE2_RXD2 80
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#define RT3883_GPIO_GE2_RXD3 81
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#define RT3883_GPIO_GE2_RXDV 82
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#define RT3883_GPIO_GE2_RXCLK 83
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#define RT3883_GPIO_GE1_TXD0 84
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#define RT3883_GPIO_GE1_TXD1 85
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#define RT3883_GPIO_GE1_TXD2 86
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#define RT3883_GPIO_GE1_TXD3 87
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#define RT3883_GPIO_GE1_TXEN 88
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#define RT3883_GPIO_GE1_TXCLK 89
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#define RT3883_GPIO_GE1_RXD0 90
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#define RT3883_GPIO_GE1_RXD1 91
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#define RT3883_GPIO_GE1_RXD2 92
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#define RT3883_GPIO_GE1_RXD3 93
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#define RT3883_GPIO_GE1_RXDV 94
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#define RT3883_GPIO_GE1_RXCLK 95
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void rt3883_gpio_init(u32 mode);
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#define RT3883_PCI_MODE_PCI 0x01
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#define RT3883_PCI_MODE_PCIE 0x02
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#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
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struct pci_dev;
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#ifdef CONFIG_PCI
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void rt3883_pci_init(unsigned mode);
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void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *));
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#else
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static inline void rt3883_pci_init(unsigned mode) {}
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static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {}
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#endif /* CONFIG_PCI */
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#endif /* _RT3883_H_ */
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