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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
135 lines
4.2 KiB
Diff
135 lines
4.2 KiB
Diff
From b2ee3bd8706521c9bbf43405c767010927c101e5 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 21 Nov 2011 17:57:51 +0100
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Subject: [PATCH 11/35] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs
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The PCI controller of the AR724X SoCs has a hardware
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bag. If the BAR0 register of the PCI device is set to
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the proper base address, the memory address space of
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the device is not accessible.
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When the device driver tries to access the memory
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address space of the PCI device, it leads to data
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bus error, similiar to this:
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Data bus error, epc == 801f69a0, ra == 801f698c
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Oops[#1]:
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Cpu 0
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$ 0 : 00000000 00000061 deadbeef 000000ff
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$ 4 : 00000000 000000ff 00000014 00000000
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$ 8 : ff000000 fffffffc 00000000 00000000
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$12 : 000001f5 00000006 00000000 6e637920
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$16 : 81ca4000 81ca0260 81ca4000 804d70f0
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$20 : fffffff4 0000002b 803ad4c4 00000000
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$24 : 00000003 00000000
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$28 : 81c20000 81c21c60 00000000 801f698c
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Hi : 00000000
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Lo : 00000000
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epc : 801f69a0 ath9k_hw_init+0xd0/0xa70
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Not tainted
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ra : 801f698c ath9k_hw_init+0xbc/0xa70
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Status: 1000c103 KERNEL EXL IE
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Cause : 1080001c
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PrId : 00019374 (MIPS 24Kc)
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Modules linked in:
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Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
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Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0
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81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b
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803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c
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00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000
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81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320
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...
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Call Trace:
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[<801f69a0>] ath9k_hw_init+0xd0/0xa70
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[<801e3ae8>] ath9k_init_device+0x174/0x680
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[<801f08a4>] ath_pci_probe+0x27c/0x380
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[<8019e490>] pci_device_probe+0x74/0x9c
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[<801bfadc>] driver_probe_device+0x9c/0x1b4
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[<801bfcb0>] __driver_attach+0xbc/0xc4
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[<801bea0c>] bus_for_each_dev+0x5c/0x98
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[<801bf394>] bus_add_driver+0x1d0/0x2a4
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[<801c0364>] driver_register+0x8c/0x16c
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[<8019e72c>] __pci_register_driver+0x4c/0xe4
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[<803d3d40>] ath9k_init+0x3c/0x88
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[<80060930>] do_one_initcall+0x3c/0x1cc
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[<803c297c>] kernel_init+0xa4/0x138
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[<80063c04>] kernel_thread_helper+0x10/0x18
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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v2: - apply the workaround on AR7240 only
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- remove unrelated defines
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---
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arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++-
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1 files changed, 35 insertions(+), 1 deletions(-)
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -9,6 +9,7 @@
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*/
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#include <linux/pci.h>
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+#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/pci.h>
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#define AR724X_PCI_CFG_BASE 0x14000000
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@@ -16,9 +17,14 @@
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x08000000
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+#define AR7240_BAR0_WAR_VALUE 0xffff
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+
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void __iomem *ar724x_pci_devcfg_base;
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+static u32 ar724x_pci_bar0_value;
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+static bool ar724x_pci_bar0_is_cached;
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+
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu
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}
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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- *value = data;
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+
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+ if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
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+ ar724x_pci_bar0_is_cached) {
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+ /* use the cached value */
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+ *value = ar724x_pci_bar0_value;
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+ } else {
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+ *value = data;
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+ }
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return PCIBIOS_SUCCESSFUL;
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}
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@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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+ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
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+ if (value != 0xffffffff) {
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+ /*
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+ * WAR for a hw issue. If the BAR0 register of the
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+ * device is set to the proper base address, the
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+ * memory space of the device is not accessible.
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+ *
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+ * Cache the intended value so it can be read back,
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+ * and write a SoC specific constant value to the
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+ * BAR0 register in order to make the device memory
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+ * accessible.
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+ */
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+ ar724x_pci_bar0_is_cached = true;
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+ ar724x_pci_bar0_value = value;
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+
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+ value = AR7240_BAR0_WAR_VALUE;
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+ } else {
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+ ar724x_pci_bar0_is_cached = false;
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+ }
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+ }
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+
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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