mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-18 13:31:55 +02:00
85ec5ce98d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29007 3c298f89-4303-0410-b956-a3cf2f4a3e73
200 lines
6.8 KiB
Diff
200 lines
6.8 KiB
Diff
From 92b24777385cd8388e0fa8b9f1d24e5bc4466641 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 13 Aug 2011 13:59:50 +0200
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Subject: [PATCH 12/22] MIPS: lantiq: make GPIO3 work on AR9
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There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack
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at 2 places to make the different register layout of the GPIO3 work properly
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with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme
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clashes with the new size, we also move the other gpio chips to new offsets.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
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arch/mips/lantiq/xway/devices.c | 3 +
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arch/mips/lantiq/xway/gpio.c | 62 ++++++++++++++++----
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arch/mips/lantiq/xway/gpio_ebu.c | 3 +-
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arch/mips/lantiq/xway/gpio_stp.c | 3 +-
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5 files changed, 57 insertions(+), 16 deletions(-)
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -121,7 +121,9 @@
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#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
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#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
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#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
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+#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0
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#define LTQ_GPIO_SIZE 0x30
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+#define LTQ_GPIO3_SIZE 0x10
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/* SSC */
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#define LTQ_SSC_BASE_ADDR 0x1e100800
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--- a/arch/mips/lantiq/xway/devices.c
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+++ b/arch/mips/lantiq/xway/devices.c
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@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource
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MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
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MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
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MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
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+ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE),
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};
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void __init ltq_register_gpio(void)
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@@ -47,6 +48,8 @@ void __init ltq_register_gpio(void)
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if (ltq_is_ar9() || ltq_is_vr9()) {
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platform_device_register_simple("ltq_gpio", 2,
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<q_gpio_resource[2], 1);
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+ platform_device_register_simple("ltq_gpio", 3,
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+ <q_gpio_resource[3], 1);
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}
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}
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--- a/arch/mips/lantiq/xway/gpio.c
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+++ b/arch/mips/lantiq/xway/gpio.c
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@@ -23,9 +23,15 @@
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#define LTQ_GPIO_OD 0x14
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#define LTQ_GPIO_PUDSEL 0x1C
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#define LTQ_GPIO_PUDEN 0x20
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+#define LTQ_GPIO3_OD 0x24
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+#define LTQ_GPIO3_ALTSEL1 0x24
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+/* PORT3 only has 8 pins and its register layout
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+ is slightly different */
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#define PINS_PER_PORT 16
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-#define MAX_PORTS 3
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+#define PINS_PORT3 8
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+#define MAX_PORTS 4
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+#define MAX_PIN 56
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#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
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#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
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@@ -55,7 +61,7 @@ int ltq_gpio_request(unsigned int pin, u
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{
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int id = 0;
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- if (pin >= (MAX_PORTS * PINS_PER_PORT))
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+ if (pin >= MAX_PIN)
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return -EINVAL;
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if (gpio_request(pin, name)) {
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pr_err("failed to setup lantiq gpio: %s\n", name);
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@@ -75,12 +81,21 @@ int ltq_gpio_request(unsigned int pin, u
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else
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ltq_gpio_clearbit(ltq_gpio_port[id].membase,
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LTQ_GPIO_ALTSEL0, pin);
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- if (alt1)
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- ltq_gpio_setbit(ltq_gpio_port[id].membase,
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- LTQ_GPIO_ALTSEL1, pin);
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- else
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- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
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- LTQ_GPIO_ALTSEL1, pin);
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+ if (id == 3) {
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+ if (alt1)
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+ ltq_gpio_setbit(ltq_gpio_port[1].membase,
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+ LTQ_GPIO3_ALTSEL1, pin);
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+ else
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+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
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+ LTQ_GPIO3_ALTSEL1, pin);
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+ } else {
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+ if (alt1)
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+ ltq_gpio_setbit(ltq_gpio_port[id].membase,
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+ LTQ_GPIO_ALTSEL1, pin);
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+ else
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+ ltq_gpio_clearbit(ltq_gpio_port[id].membase,
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+ LTQ_GPIO_ALTSEL1, pin);
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+ }
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return 0;
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}
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EXPORT_SYMBOL(ltq_gpio_request);
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@@ -106,7 +121,11 @@ static int ltq_gpio_direction_input(stru
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{
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struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
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- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
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+ if (chip->ngpio == PINS_PORT3)
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+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
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+ LTQ_GPIO3_OD, offset);
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+ else
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+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
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ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
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ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
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ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
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@@ -119,7 +138,10 @@ static int ltq_gpio_direction_output(str
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{
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struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
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- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
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+ if (chip->ngpio == PINS_PORT3)
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+ ltq_gpio_setbit(ltq_gpio_port[0].membase, LTQ_GPIO3_OD, offset);
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+ else
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+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
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ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
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ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
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ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
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@@ -133,7 +155,11 @@ static int ltq_gpio_req(struct gpio_chip
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struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
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ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
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- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
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+ if (chip->ngpio == PINS_PORT3)
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+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
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+ LTQ_GPIO3_ALTSEL1, offset);
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+ else
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+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
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return 0;
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}
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@@ -146,6 +172,15 @@ static int ltq_gpio_probe(struct platfor
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pdev->id);
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return -EINVAL;
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}
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+
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+ /* dirty hack - The registers of port3 are not mapped linearly.
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+ Port 3 may only load if Port 1/2 are mapped */
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+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase || !ltq_gpio_port[2].membase)) {
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+ dev_err(&pdev->dev,
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+ "ports 1/2 need to be loaded before port 3 works\n");
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+ return -ENOMEM;
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+ }
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+
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
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@@ -175,7 +210,10 @@ static int ltq_gpio_probe(struct platfor
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ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
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ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
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ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
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- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
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+ if (pdev->id == 3)
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+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3;
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+ else
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+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
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platform_set_drvdata(pdev, <q_gpio_port[pdev->id]);
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return gpiochip_add(<q_gpio_port[pdev->id].chip);
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}
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--- a/arch/mips/lantiq/xway/gpio_ebu.c
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+++ b/arch/mips/lantiq/xway/gpio_ebu.c
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@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
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.label = "ltq_ebu",
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.direction_output = ltq_ebu_direction_output,
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.set = ltq_ebu_set,
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- .base = 72,
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+ .base = 100,
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.ngpio = 16,
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- .can_sleep = 1,
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.owner = THIS_MODULE,
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};
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--- a/arch/mips/lantiq/xway/gpio_stp.c
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+++ b/arch/mips/lantiq/xway/gpio_stp.c
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@@ -72,9 +72,8 @@ static struct gpio_chip ltq_stp_chip = {
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.label = "ltq_stp",
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.direction_output = ltq_stp_direction_output,
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.set = ltq_stp_set,
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- .base = 48,
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+ .base = 200,
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.ngpio = 24,
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- .can_sleep = 1,
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.owner = THIS_MODULE,
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};
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