mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-19 01:17:42 +03:00
12a0868f92
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24087 3c298f89-4303-0410-b956-a3cf2f4a3e73
243 lines
9.7 KiB
C
243 lines
9.7 KiB
C
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#define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000)
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#define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800)
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/*
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#define FEC_INTC_IMRH_INT_MASK38 (0x00000040)
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#define FEC_INTC_IMRH_INT_MASK39 (0x00000080)
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#define FEC_INTC_ICR_FEC0 (0x30)
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#define FEC_INTC_ICR_FEC1 (0x31)
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*/
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#define FEC_FECI2CIRQ (0xFFC0)
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#define FEC_GPIO_PAR_FECI2CIRQ \
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(*(volatile unsigned short *)((unsigned int)MCF_MBAR + 0xA44))
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/*
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#define FEC_INTC_ICRn(x) \
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(*(volatile unsigned char *)(void*)
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((unsigned int) MCF_MBAR + 0x000740+((x)*0x001)))
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#define FEC_INTC_IMRH \
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*(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708)
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*/
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#define FEC_ECR_DISABLE (0x00000000)
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#define FEC_ECR(x) \
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(*(volatile unsigned int *)(x + 0x024))
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#define FEC_EIR(x) \
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(*(volatile unsigned int *)(x + 0x004))
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#define FEC_PALR(x) \
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(*(volatile unsigned int *)(x + 0x0E4))
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#define FEC_PAUR(x) \
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(*(volatile unsigned int *)(x + 0x0E8))
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#define FEC_IALR(x) \
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(*(volatile unsigned int *)(x + 0x11C))
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#define FEC_IAUR(x) \
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(*(volatile unsigned int *)(x + 0x118))
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#define FEC_GALR(x) \
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(*(volatile unsigned int *)(x + 0x124))
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#define FEC_GAUR(x) \
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(*(volatile unsigned int *)(x + 0x120))
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#define FEC_RCR(x) \
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(*(volatile unsigned int *)(x + 0x084))
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#define FEC_FECRFCR(x) \
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(*(volatile unsigned int *)(x + 0x18C))
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#define FEC_FECRFAR(x) \
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(*(volatile unsigned int *)(x + 0x198))
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#define FEC_FECTFCR(x) \
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(*(volatile unsigned int *)(x + 0x1AC))
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#define FEC_FECTFAR(x) \
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(*(volatile unsigned int *)(x + 0x1B8))
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#define FEC_FECTFWR(x) \
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(*(volatile unsigned int *)(x + 0x144))
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#define FEC_CTCWR(x) \
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(*(volatile unsigned int *)(x + 0x1C8))
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#define FEC_EIMR(x) \
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(*(volatile unsigned int *)(x + 0x008))
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#define FEC_TCR(x) \
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(*(volatile unsigned int *)(x + 0x0C4))
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#define FEC_MIBC(x) \
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(*(volatile unsigned int *)(x + 0x064))
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#define FEC_MSCR(x) \
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(*(volatile unsigned int *)(x + 0x044))
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#define FEC_FECTFDR(x) \
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(*(volatile unsigned int *)(x + 0x1A4))
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#define FEC_FECRFDR(x) \
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(*(volatile unsigned int *)(x + 0x184))
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#define FEC_FECTFSR(x) \
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(*(volatile unsigned int *)(x + 0x1A8))
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#define FEC_FECRFSR(x) \
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(*(volatile unsigned int *)(x + 0x188))
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#define FECSTAT_RMON_R_PACKETS(x) \
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(*(volatile unsigned int *)(x + 0x284))
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#define FECSTAT_RMON_T_PACKETS(x) \
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(*(volatile unsigned int *)(x + 0x204))
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#define FECSTAT_RMON_R_OCTETS(x) \
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(*(volatile unsigned int *)(x + 0x2C4))
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#define FECSTAT_RMON_T_OCTETS(x) \
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(*(volatile unsigned int *)(x + 0x244))
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#define FECSTAT_RMON_R_UNDERSIZE(x) \
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(*(volatile unsigned int *)(x + 0x294))
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#define FECSTAT_RMON_R_OVERSIZE(x) \
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(*(volatile unsigned int *)(x + 0x298))
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#define FECSTAT_RMON_R_FRAG(x) \
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(*(volatile unsigned int *)(x + 0x29C))
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#define FECSTAT_RMON_R_JAB(x) \
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(*(volatile unsigned int *)(x + 0x2A0))
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#define FECSTAT_RMON_R_MC_PKT(x) \
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(*(volatile unsigned int *)(x + 0x28C))
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#define FECSTAT_RMON_T_COL(x) \
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(*(volatile unsigned int *)(x + 0x224))
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#define FECSTAT_IEEE_R_ALIGN(x) \
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(*(volatile unsigned int *)(x + 0x2D4))
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#define FECSTAT_IEEE_R_CRC(x) \
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(*(volatile unsigned int *)(x + 0x2D0))
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#define FECSTAT_IEEE_R_MACERR(x) \
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(*(volatile unsigned int *)(x + 0x2D8))
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#define FECSTAT_IEEE_T_CSERR(x) \
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(*(volatile unsigned int *)(x + 0x268))
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#define FECSTAT_IEEE_T_MACERR(x) \
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(*(volatile unsigned int *)(x + 0x264))
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#define FECSTAT_IEEE_T_LCOL(x) \
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(*(volatile unsigned int *)(x + 0x25C))
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#define FECSTAT_IEEE_R_OCTETS_OK(x) \
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(*(volatile unsigned int *)(x + 0x2E0))
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#define FECSTAT_IEEE_T_OCTETS_OK(x) \
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(*(volatile unsigned int *)(x + 0x274))
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#define FECSTAT_IEEE_R_DROP(x) \
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(*(volatile unsigned int *)(x + 0x2C8))
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#define FECSTAT_IEEE_T_DROP(x) \
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(*(volatile unsigned int *)(x + 0x248))
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#define FECSTAT_IEEE_R_FRAME_OK(x) \
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(*(volatile unsigned int *)(x + 0x2CC))
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#define FECSTAT_IEEE_T_FRAME_OK(x) \
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(*(volatile unsigned int *)(x + 0x24C))
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#define FEC_MMFR(x) \
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(*(volatile unsigned int *)(x + 0x040))
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#define FEC_FECFRST(x) \
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(*(volatile unsigned int *)(x + 0x1C4))
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#define FEC_MAX_FRM_SIZE (1518)
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#define FEC_MAXBUF_SIZE (1520)
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/* Register values */
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#define FEC_ECR_RESET (0x00000001)
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#define FEC_EIR_CLEAR (0xFFFFFFFF)
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#define FEC_EIR_RL (0x00100000)
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#define FEC_EIR_HBERR (0x80000000)
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#define FEC_EIR_BABR (0x40000000)
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/* babbling receive error */
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#define FEC_EIR_BABT (0x20000000)
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/* babbling transmit error */
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#define FEC_EIR_TXF (0x08000000)
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/* transmit frame interrupt */
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#define FEC_EIR_MII (0x00800000)
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/* MII interrupt */
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#define FEC_EIR_LC (0x00200000)
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/* late collision */
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#define FEC_EIR_XFUN (0x00080000)
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/* transmit FIFO underrun */
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#define FEC_EIR_XFERR (0x00040000)
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/* transmit FIFO error */
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#define FEC_EIR_RFERR (0x00020000)
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/* receive FIFO error */
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#define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16)
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#define FEC_RCR_MII (0x00000004)
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#define FEC_FECRFCR_FAE (0x00400000)
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/* frame accept error */
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#define FEC_FECRFCR_RXW (0x00200000)
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/* receive wait condition */
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#define FEC_FECRFCR_UF (0x00100000)
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/* receive FIFO underflow */
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#define FEC_FECRFCR_FRM (0x08000000)
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#define FEC_FECRFCR_GR (0x7 << 24)
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#define FEC_EIMR_DISABLE (0x00000000)
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#define FEC_FECRFAR_ALARM (0x300)
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#define FEC_FECTFCR_FRM (0x08000000)
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#define FEC_FECTFCR_GR (0x7 << 24)
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#define FEC_FECTFCR_FAE (0x00400000)
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/* frame accept error */
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#define FEC_FECTFCR_TXW (0x00040000)
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/* transmit wait condition */
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#define FEC_FECTFCR_UF (0x00100000)
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/* transmit FIFO underflow */
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#define FEC_FECTFCR_OF (0x00080000)
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/* transmit FIFO overflow */
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#define FEC_FECTFAR_ALARM (0x100)
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#define FEC_FECTFWR_XWMRK (0x00000000)
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#define FEC_FECTFSR_MSK (0xC0B00000)
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#define FEC_FECTFSR_TXW (0x40000000)
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/* transmit wait condition */
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#define FEC_FECTFSR_FAE (0x00800000)
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/* frame accept error */
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#define FEC_FECTFSR_UF (0x00200000)
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/* transmit FIFO underflow */
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#define FEC_FECTFSR_OF (0x00100000)
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/* transmit FIFO overflow */
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#define FEC_FECRFSR_MSK (0x80F00000)
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#define FEC_FECRFSR_FAE (0x00800000)
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/* frame accept error */
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#define FEC_FECRFSR_RXW (0x00400000)
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/* receive wait condition */
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#define FEC_FECRFSR_UF (0x00200000)
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/* receive FIFO underflow */
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#define FEC_CTCWR_TFCW_CRC (0x03000000)
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#define FEC_TCR_FDEN (0x00000004)
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#define FEC_TCR_HBC (0x00000002)
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#define FEC_RCR_DRT (0x00000002)
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#define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR)
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#define FEC_ECR_ETHEREN (0x00000002)
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#define FEC_FECTFCR_MSK (0x00FC0000)
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#define FEC_FECRFCR_MSK (0x00F80000)
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#define FEC_EIR_GRA (0x10000000)
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#define FEC_TCR_GTS (0x00000001)
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#define FEC_MIBC_ENABLE (0x00000000)
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#define FEC_MIB_LEN (228)
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#define FEC_PHY_ADDR (0x01)
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#define FEC_RX_DMA_PRI (6)
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#define FEC_TX_DMA_PRI (6)
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#define FEC_TX_BUF_NUMBER (8)
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#define FEC_RX_BUF_NUMBER (64)
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#define FEC_TX_INDEX_MASK (0x7)
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#define FEC_RX_INDEX_MASK (0x3f)
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#define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START
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#define FEC_TX_DESC_FEC0 \
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(FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec))
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#define FEC_RX_DESC_FEC1 \
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(SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2)
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#define FEC_TX_DESC_FEC1 \
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(FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec))
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#define FEC_EIR_MII (0x00800000)
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#define FEC_MMFR_READ (0x60020000)
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#define FEC_MMFR_WRITE (0x50020000)
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#define FEC_FLAGS_RX (0x00000001)
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#define FEC_CRCPOL (0xEDB88320)
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#define FEC_MII_TIMEOUT (2)
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#define FEC_GR_TIMEOUT (1)
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#define FEC_TX_TIMEOUT (1)
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#define FEC_RX_TIMEOUT (1)
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#define FEC_SW_RST 0x2000000
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#define FEC_RST_CTL 0x1000000
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int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
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unsigned int *data);
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int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
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unsigned int data);
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#define FEC_MII_SPEED \
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((MCF_CLK / 2) / ((2500000 / 2) * 2))
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