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df88996997
The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
109 lines
3.0 KiB
Diff
109 lines
3.0 KiB
Diff
From e63ceaa0c4f7be0498cd452981073d3ce8e7d1f5 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 9 Jan 2012 15:00:46 +0100
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Subject: [PATCH 32/34] spi/ath79: avoid multiple initialization of the SPI controller
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Currently we are initializing the SPI controller in
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the chip select line function, and that function is
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called once for each SPI device on the bus. If a
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board has multiple SPI devices, the controller will
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be initialized multiple times.
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Introduce ath79_spi_{en,dis}able helper functions,
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and call those from probe/response in order to avoid
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the mutliple initialization of the controller.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++-----------------
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1 files changed, 24 insertions(+), 17 deletions(-)
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
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}
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-static int ath79_spi_setup_cs(struct spi_device *spi)
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+static void ath79_spi_enable(struct ath79_spi *sp)
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{
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- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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- struct ath79_spi_controller_data *cdata;
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- int status;
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-
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- cdata = spi->controller_data;
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- if (spi->chip_select && !cdata)
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- return -EINVAL;
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-
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/* enable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
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/* TODO: setup speed? */
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ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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+}
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+
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+static void ath79_spi_disable(struct ath79_spi *sp)
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+{
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+ /* restore CTRL register */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
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+ /* disable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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+}
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+
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+static int ath79_spi_setup_cs(struct spi_device *spi)
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+{
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+ struct ath79_spi_controller_data *cdata;
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+ int status;
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+
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+ cdata = spi->controller_data;
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+ if (spi->chip_select && !cdata)
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+ return -EINVAL;
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status = 0;
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if (spi->chip_select) {
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@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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-
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if (spi->chip_select) {
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struct ath79_spi_controller_data *cdata = spi->controller_data;
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gpio_free(cdata->gpio);
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}
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-
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- /* restore CTRL register */
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- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
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- /* disable GPIO mode */
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- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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}
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static int ath79_spi_setup(struct spi_device *spi)
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@@ -268,12 +271,15 @@ static __devinit int ath79_spi_probe(str
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dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
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sp->rrw_delay);
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+ ath79_spi_enable(sp);
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ret = spi_bitbang_start(&sp->bitbang);
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if (ret)
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- goto err_clk_disable;
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+ goto err_disable;
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return 0;
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+err_disable:
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+ ath79_spi_disable(sp);
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err_clk_disable:
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clk_disable(sp->clk);
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err_clk_put:
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@@ -292,6 +298,7 @@ static __devexit int ath79_spi_remove(st
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struct ath79_spi *sp = platform_get_drvdata(pdev);
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spi_bitbang_stop(&sp->bitbang);
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+ ath79_spi_disable(sp);
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clk_disable(sp->clk);
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clk_put(sp->clk);
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iounmap(sp->base);
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