mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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cea2b4210d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32953 3c298f89-4303-0410-b956-a3cf2f4a3e73
131 lines
5.8 KiB
C
131 lines
5.8 KiB
C
/******************************************************************************
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Copyright (c) 2007
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Infineon Technologies AG
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St. Martin Strasse 53; 81669 Munich, Germany
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Any use of this Software is subject to the conclusion of a respective
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License Agreement. Without such a License Agreement no rights to the
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Software are granted.
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******************************************************************************/
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#ifndef __STATUS_REG_H
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#define __STATUS_REG_H
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#define status_r32(reg) ltq_r32(&status->reg)
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#define status_w32(val, reg) ltq_w32(val, &status->reg)
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#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg)
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/** STATUS register structure */
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struct svip_reg_status {
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unsigned long fuse_deu; /* 0x0000 */
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unsigned long fuse_cpu; /* 0x0004 */
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unsigned long fuse_pll; /* 0x0008 */
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unsigned long chipid; /* 0x000C */
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unsigned long config; /* 0x0010 */
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unsigned long chip_loc; /* 0x0014 */
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unsigned long fuse_spare; /* 0x0018 */
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};
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/*******************************************************************************
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* Fuse for DEU Settings
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******************************************************************************/
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/* Fuse for Enabling the TRNG (6) */
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#define STATUS_FUSE_DEU_TRNG (0x1 << 6)
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#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1)
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/* Fuse for Enabling the DES Submodule (5) */
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#define STATUS_FUSE_DEU_DES (0x1 << 5)
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#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1)
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/* Fuse for Enabling the 3DES Submodule (4) */
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#define STATUS_FUSE_DEU_3DES (0x1 << 4)
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#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1)
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/* Fuse for Enabling the AES Submodule (3) */
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#define STATUS_FUSE_DEU_AES (0x1 << 3)
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#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1)
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/* Fuse for Enabling the HASH Submodule (2) */
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#define STATUS_FUSE_DEU_HASH (0x1 << 2)
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#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1)
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/* Fuse for Enabling the ARC4 Submodule (1) */
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#define STATUS_FUSE_DEU_ARC4 (0x1 << 1)
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#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1)
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/* Fuse for Enabling the DEU Module (0) */
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#define STATUS_FUSE_DEU_DEU (0x1)
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#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1)
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/*******************************************************************************
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* Fuse for CPU Settings
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******************************************************************************/
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/* Fuse for Enabling CPU5 (5) */
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#define STATUS_FUSE_CPU_CPU5 (0x1 << 5)
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#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1)
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/* Fuse for Enabling the CPU4 (4) */
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#define STATUS_FUSE_CPU_CPU4 (0x1 << 4)
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#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1)
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/* Fuse for Enabling the CPU3 (3) */
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#define STATUS_FUSE_CPU_CPU3 (0x1 << 3)
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#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1)
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/* Fuse for Enabling the CPU2 (2) */
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#define STATUS_FUSE_CPU_CPU2 (0x1 << 2)
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#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1)
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/* Fuse for Enabling the CPU1 (1) */
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#define STATUS_FUSE_CPU_CPU1 (0x1 << 1)
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#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1)
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/* Fuse for Enabling the CPU0 (0) */
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#define STATUS_FUSE_CPU_CPU0 (0x1)
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#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1)
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/*******************************************************************************
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* Fuse for PLL Settings
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******************************************************************************/
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/* Fuse for Enabling PLL (7:0) */
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#define STATUS_FUSE_PLL_PLL (0xff)
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#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff)
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/*******************************************************************************
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* Chip Identification Register
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******************************************************************************/
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/* Chip Version Number (31:28) */
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#define STATUS_CHIPID_VERSION (0xf << 28)
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#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf)
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/* Part Number (27:12) */
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#define STATUS_CHIPID_PART_NUMBER (0xffff << 12)
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#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff)
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/* Manufacturer ID (11:1) */
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#define STATUS_CHIPID_MANID (0x7ff << 1)
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#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff)
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/*******************************************************************************
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* Chip Configuration Register
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******************************************************************************/
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/* Number of Analog Channels (8:5) */
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#define STATUS_CONFIG_ANA_CHAN (0xf << 5)
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#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf)
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/* Clock Mode (4) */
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#define STATUS_CONFIG_CLK_MODE (0x1 << 1)
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#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1)
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/* Subversion Number (3:0) */
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#define STATUS_CONFIG_SUB_VERS (0xF)
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#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF)
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/*******************************************************************************
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* Chip Location Register
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******************************************************************************/
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/* Chip Lot ID (31:16) */
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#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16)
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#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff)
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/* Chip X Coordinate (15:8) */
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#define STATUS_CHIP_LOC_CHIP_X (0xff << 8)
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#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff)
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/* Chip Y Coordinate (7:0) */
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#define STATUS_CHIP_LOC_CHIP_Y (0xff)
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#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff)
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#endif
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