mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-21 06:10:50 +02:00
5478db1fd5
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26911 3c298f89-4303-0410-b956-a3cf2f4a3e73
78 lines
2.4 KiB
Diff
78 lines
2.4 KiB
Diff
--- a/drivers/ssb/driver_pcicore.c
|
|
+++ b/drivers/ssb/driver_pcicore.c
|
|
@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
|
|
pcicore_write32(pc, mdio_control, 0);
|
|
}
|
|
|
|
-static void ssb_broadcast_value(struct ssb_device *dev,
|
|
- u32 address, u32 data)
|
|
-{
|
|
- /* This is used for both, PCI and ChipCommon core, so be careful. */
|
|
- BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
|
|
- BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
|
|
-
|
|
- ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
|
|
- ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
|
|
- ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
|
|
- ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
|
|
-}
|
|
-
|
|
-static void ssb_commit_settings(struct ssb_bus *bus)
|
|
-{
|
|
- struct ssb_device *dev;
|
|
-
|
|
- dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
|
|
- if (WARN_ON(!dev))
|
|
- return;
|
|
- /* This forces an update of the cached registers. */
|
|
- ssb_broadcast_value(dev, 0xFD8, 0);
|
|
-}
|
|
-
|
|
int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
|
|
struct ssb_device *dev)
|
|
{
|
|
--- a/drivers/ssb/main.c
|
|
+++ b/drivers/ssb/main.c
|
|
@@ -1330,6 +1330,31 @@ error:
|
|
}
|
|
EXPORT_SYMBOL(ssb_bus_powerup);
|
|
|
|
+static void ssb_broadcast_value(struct ssb_device *dev,
|
|
+ u32 address, u32 data)
|
|
+{
|
|
+ /* This is used for both, PCI and ChipCommon core, so be careful. */
|
|
+ BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
|
|
+ BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
|
|
+
|
|
+ ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
|
|
+ ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
|
|
+ ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
|
|
+ ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
|
|
+}
|
|
+
|
|
+void ssb_commit_settings(struct ssb_bus *bus)
|
|
+{
|
|
+ struct ssb_device *dev;
|
|
+
|
|
+ dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
|
|
+ if (WARN_ON(!dev))
|
|
+ return;
|
|
+ /* This forces an update of the cached registers. */
|
|
+ ssb_broadcast_value(dev, 0xFD8, 0);
|
|
+}
|
|
+EXPORT_SYMBOL(ssb_commit_settings);
|
|
+
|
|
u32 ssb_admatch_base(u32 adm)
|
|
{
|
|
u32 base = 0;
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct
|
|
* Otherwise static always-on powercontrol will be used. */
|
|
extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
|
|
|
|
+extern void ssb_commit_settings(struct ssb_bus *bus);
|
|
|
|
/* Various helper functions */
|
|
extern u32 ssb_admatch_base(u32 adm);
|