mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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0a2b2965cd
* bump kernel to 2.6.35.8 * merge arcadyn mach files * fixes ar9 * adds hack for tapi drivers git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23836 3c298f89-4303-0410-b956-a3cf2f4a3e73
145 lines
4.8 KiB
C
Executable File
145 lines
4.8 KiB
C
Executable File
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
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* Copyright (C) 2009 Mohammad Firdaus
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*/
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/*!
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\defgroup IFX_DEU IFX_DEU_DRIVERS
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\ingroup API
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\brief ifx deu driver module
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*/
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/*!
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\file ifxmips_deu.h
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\brief main deu driver header file
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*/
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/*!
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\defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
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\ingroup IFX_DEU
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\brief ifx deu definitions
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*/
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#ifndef IFXMIPS_DEU_H
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#define IFXMIPS_DEU_H
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#define IFX_DEU_DRV_VERSION "1.0.1"
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#include "ifxmips_deu_danube.h"
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#define IFXDEU_ALIGNMENT 16
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#define PFX "ifxdeu: "
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#define IFXDEU_CRA_PRIORITY 300
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#define IFXDEU_COMPOSITE_PRIORITY 400
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#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100)
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#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))
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#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008))
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#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))
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#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))
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#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))
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#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))
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#define IFX_DEU_ID_REV 0x00001F
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#define IFX_DEU_ID_ID 0x00FF00
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#define IFX_DEU_ID_DMA 0x010000
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#define IFX_DEU_ID_HASH 0x020000
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#define IFX_DEU_ID_AES 0x040000
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#define IFX_DEU_ID_3DES 0x080000
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#define IFX_DEU_ID_DES 0x100000
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#define CRYPTO_DIR_ENCRYPT 1
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#define CRYPTO_DIR_DECRYPT 0
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#undef CRYPTO_DEBUG
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#ifdef CRYPTO_DEBUG
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extern char deu_debug_level;
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#define DPRINTF(level, format, args...) if (level < deu_debug_level) printk(KERN_INFO "[%s %s %d]: " format, __FILE__, __func__, __LINE__, ##args);
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#else
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#define DPRINTF(level, format, args...)
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#endif
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#define IFX_MPS (KSEG1 | 0x1F107000)
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#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344))
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#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF)
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#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28)
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#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF)
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#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12)
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#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF)
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#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1)
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void chip_version(void);
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int __init ifxdeu_init_des (void);
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int __init ifxdeu_init_aes (void);
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int __init ifxdeu_init_arc4 (void);
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int __init ifxdeu_init_sha1 (void);
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int __init ifxdeu_init_md5 (void);
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int __init ifxdeu_init_sha1_hmac (void);
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int __init ifxdeu_init_md5_hmac (void);
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void __exit ifxdeu_fini_des (void);
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void __exit ifxdeu_fini_aes (void);
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void __exit ifxdeu_fini_arc4 (void);
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void __exit ifxdeu_fini_sha1 (void);
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void __exit ifxdeu_fini_md5 (void);
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void __exit ifxdeu_fini_sha1_hmac (void);
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void __exit ifxdeu_fini_md5_hmac (void);
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void __exit ifxdeu_fini_dma(void);
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int deu_dma_init (void);
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#define DEU_WAKELIST_INIT(queue) \
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init_waitqueue_head(&queue)
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#define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout) \
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do { \
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wait_event_interruptible_timeout((queue), \
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test_bit((event), &(flags)), (timeout)); \
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clear_bit((event), &(flags)); \
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}while (0)
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#define DEU_WAKEUP_EVENT(queue, event, flags) \
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do { \
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set_bit((event), &(flags)); \
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wake_up_interruptible(&(queue)); \
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}while (0)
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#define DEU_WAIT_EVENT(queue, event, flags) \
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do { \
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wait_event_interruptible(queue, \
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test_bit((event), &(flags))); \
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clear_bit((event), &(flags)); \
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}while (0)
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typedef struct deu_drv_priv {
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wait_queue_head_t deu_thread_wait;
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#define DEU_EVENT 1
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volatile long deu_event_flags;
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u8 *deu_rx_buf;
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u32 deu_rx_len;
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}deu_drv_priv_t;
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#endif /* IFXMIPS_DEU_H */
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