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293a2a0958
uboot-xburst-avt2 uboot-xburst-n516 uboot-xburst-qi_lb60 uboot-xburst-sakc Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
29 lines
1.1 KiB
C
29 lines
1.1 KiB
C
#ifndef __CONFIG_QI_LB60_H
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#define __CONFIG_QI_LB60_H
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#include <configs/nanonote.h>
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#define CONFIG_QI_LB60 1
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//#define DEBUG
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#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
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#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
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#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
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#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm"
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/* SDRAM paramters */
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#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
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#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define SDRAM_ROW 13 /* Row address: 11 to 13 */
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#define SDRAM_COL 9 /* Column address: 8 to 12 */
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#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
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/* SDRAM Timings, unit: ns */
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#define SDRAM_TRAS 45 /* RAS# Active Time */
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
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#endif
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