mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31602 3c298f89-4303-0410-b956-a3cf2f4a3e73
195 lines
6.0 KiB
Diff
195 lines
6.0 KiB
Diff
From b16fdecf14d24fe213c81409c0c2dca66d5b7bc9 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 14 Mar 2012 10:45:25 +0100
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Subject: [PATCH 30/47] MIPS: ath79: add IRQ handling code for AR934X
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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Cc: linux-mips@linux-mips.org
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Cc: mcgrof@infradead.org
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Patchwork: https://patchwork.linux-mips.org/patch/3510/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
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arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
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3 files changed, 83 insertions(+), 3 deletions(-)
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -1,10 +1,11 @@
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/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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- * Parts of this file are based on Atheros' 2.6.15 BSP
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+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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- else if (soc_is_ar724x() || soc_is_ar933x())
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+ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
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irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
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}
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+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ disable_irq_nosync(irq);
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+
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+ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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+
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+ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
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+ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
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+ generic_handle_irq(ATH79_IP2_IRQ(1));
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+ } else {
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+ spurious_interrupt();
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+ }
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+
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+ enable_irq(irq);
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+}
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+
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+static void ar934x_ip2_irq_init(void)
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+{
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+ int i;
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+
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+ for (i = ATH79_IP2_IRQ_BASE;
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+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip,
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+ handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
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+}
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+
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
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do_IRQ(ATH79_CPU_IRQ_IP2);
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}
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+static void ar934x_ip2_handler(void)
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+{
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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static void ar71xx_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
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@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
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do_IRQ(ATH79_CPU_IRQ_USB);
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}
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+static void ar934x_ip3_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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void __init arch_init_irq(void)
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{
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if (soc_is_ar71xx()) {
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@@ -240,6 +285,9 @@ void __init arch_init_irq(void)
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} else if (soc_is_ar933x()) {
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ath79_ip2_handler = ar933x_ip2_handler;
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ath79_ip3_handler = ar933x_ip3_handler;
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+ } else if (soc_is_ar934x()) {
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+ ath79_ip2_handler = ar934x_ip2_handler;
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+ ath79_ip3_handler = ar934x_ip3_handler;
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} else {
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BUG();
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}
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@@ -247,4 +295,7 @@ void __init arch_init_irq(void)
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cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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+
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+ if (soc_is_ar934x())
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+ ar934x_ip2_irq_init();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -92,6 +92,12 @@
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#define AR933X_DDR_REG_FLUSH_USB 0x84
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#define AR933X_DDR_REG_FLUSH_WMAC 0x88
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+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
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+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
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+#define AR934X_DDR_REG_FLUSH_USB 0xa4
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+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
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+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
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+
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/*
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* PLL block
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*/
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@@ -222,6 +228,7 @@
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#define AR933X_RESET_REG_BOOTSTRAP 0xac
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#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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@@ -295,6 +302,24 @@
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#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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#define AR934X_BOOTSTRAP_DDR1 BIT(0)
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+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
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+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
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+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
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+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
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+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
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+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
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+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
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+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
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+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
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+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
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+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
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+
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+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
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+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
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+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
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+
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -10,7 +10,7 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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-#define NR_IRQS 46
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+#define NR_IRQS 48
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#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
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@@ -19,6 +19,10 @@
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#define ATH79_PCI_IRQ_COUNT 6
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#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
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+#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
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+#define ATH79_IP2_IRQ_COUNT 2
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+#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
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+
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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