mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-07 20:07:32 +02:00
1d5d64e647
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7722 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
#ifndef __DIAG_GPIO_H
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#define __DIAG_GPIO_H
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#include <linux/interrupt.h>
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#ifndef BCMDRIVER
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/ssb/ssb_driver_extif.h>
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extern struct ssb_bus ssb;
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#define gpio_op(op, param...) \
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do { \
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if (ssb.chipco.dev) \
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return ssb_chipco_gpio_##op(&ssb.chipco, param); \
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else if (ssb.extif.dev) \
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return ssb_extif_gpio_##op(&ssb.extif, param); \
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else \
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return 0; \
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} while (0);
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static inline u32 gpio_in(void)
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{
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gpio_op(in, ~0);
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}
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static inline u32 gpio_out(u32 mask, u32 value)
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{
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gpio_op(out, mask, value);
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}
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static inline u32 gpio_outen(u32 mask, u32 value)
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{
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gpio_op(outen, mask, value);
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}
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static inline u32 gpio_control(u32 mask, u32 value)
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{
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if (ssb.chipco.dev)
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return ssb_chipco_gpio_control(&ssb.chipco, mask, value);
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else
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return 0;
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}
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static inline u32 gpio_intmask(u32 mask, u32 value)
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{
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gpio_op(intmask, mask, value);
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}
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static inline u32 gpio_intpolarity(u32 mask, u32 value)
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{
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gpio_op(polarity, mask, value);
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}
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static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
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{
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int irq;
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if (ssb.chipco.dev)
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irq = ssb_mips_irq(ssb.chipco.dev) + 2;
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else if (ssb.extif.dev)
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irq = ssb_mips_irq(ssb.extif.dev) + 2;
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else return;
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if (enabled) {
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if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
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return;
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} else {
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free_irq(irq, handler);
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}
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if (ssb.chipco.dev)
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ssb_write32_masked(ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
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}
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#else
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#include <typedefs.h>
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#include <osl.h>
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#include <bcmdevs.h>
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#include <sbutils.h>
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#include <sbconfig.h>
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#include <sbchipc.h>
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
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#include <sbmips.h>
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#else
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#include <hndcpu.h>
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
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#define sbh bcm947xx_sbh
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#define sbh_lock bcm947xx_sbh_lock
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#endif
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extern void *sbh;
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extern spinlock_t sbh_lock;
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#define gpio_in() sb_gpioin(sbh)
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#define gpio_out(mask, value) sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
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#define gpio_outen(mask, value) sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
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#define gpio_control(mask, value) sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
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#define gpio_intmask(mask, value) sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
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#define gpio_intpolarity(mask, value) sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
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static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
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{
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unsigned int coreidx;
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unsigned long flags;
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chipcregs_t *cc;
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int irq;
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spin_lock_irqsave(sbh_lock, flags);
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coreidx = sb_coreidx(sbh);
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irq = sb_irq(sbh) + 2;
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if (enabled)
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request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
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else
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free_irq(irq, handler);
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if ((cc = sb_setcore(sbh, SB_CC, 0))) {
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int intmask;
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intmask = readl(&cc->intmask);
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if (enabled)
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intmask |= CI_GPIO;
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else
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intmask &= ~CI_GPIO;
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writel(intmask, &cc->intmask);
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}
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sb_setcoreidx(sbh, coreidx);
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spin_unlock_irqrestore(sbh_lock, flags);
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}
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#endif /* BCMDRIVER */
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#define EXTIF_ADDR 0x1f000000
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#define EXTIF_UART (EXTIF_ADDR + 0x00800000)
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#define GPIO_TYPE_NORMAL (0x0 << 24)
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#define GPIO_TYPE_EXTIF (0x1 << 24)
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#define GPIO_TYPE_MASK (0xf << 24)
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static inline void gpio_set_extif(int gpio, int value)
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{
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volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
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if (value)
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*addr = 0xFF;
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else
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*addr;
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}
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#endif /* __DIAG_GPIO_H */
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