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ed42a8a323
flash write routine is not functional yet add configuration (board & dram) git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20603 3c298f89-4303-0410-b956-a3cf2f4a3e73
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file contains the configuration parameters for the Danube reference board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* #define DEBUG */
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#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
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#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
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#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
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#define CONFIG_EASY50712 1 /* on the Danube Reference Board */
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#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
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#define CONFIG_SYS_MAX_RAM 32*1024*1024
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
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#ifdef CONFIG_SYS_RAMBOOT
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//#warning CONFIG_SYS_RAMBOOT
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#else /* CONFIG_SYS_RAMBOOT */
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#define CONFIG_SYS_EBU_BOOT
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#ifdef CONFIG_USE_DDR_RAM
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/* FIXME: should not need these workarounds */
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#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
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#endif
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#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
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#endif /* CONFIG_SYS_RAMBOOT */
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#if 1
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#ifndef CPU_CLOCK_RATE
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#define CPU_CLOCK_RATE (ifx_get_cpuclk())
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#endif
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#endif
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#define CONFIG_SYS_PROMPT "DANUBE => " /* Monitor Command Prompt */
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#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
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/*
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* Include common defines/options for all Infineon boards
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*/
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#include "ifx-common.h"
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/*
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* Cache Configuration (cpu/chip specific, Danube)
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*/
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#define CONFIG_SYS_DCACHE_SIZE 16384
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#define CONFIG_SYS_ICACHE_SIZE 16384
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
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#define CONFIG_NET_MULTI
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#if 0
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#define CONFIG_M4530_ETH
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#define CONFIG_M4530_FPGA
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#endif
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#define CONFIG_IFX_ETOP
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#define CLK_OUT2_25MHZ
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#define CONFIG_EXTRA_SWITCH
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#define CONFIG_RMII /* use interface in RMII mode */
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_IFX_ASC
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#ifdef CONFIG_USE_ASC0
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#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
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#else
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#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
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#endif
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#ifdef CONFIG_SYS_RAMBOOT
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/* Configuration of EBU: */
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/* starting address from 0xb0000000 */
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/* make the flash available from RAM boot */
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# define CONFIG_EBU_ADDSEL0 0x10000031
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# define CONFIG_EBU_BUSCON0 0x0001D7FF
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#endif
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#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
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#endif /* __CONFIG_H */
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