openwrt-xburst/target/linux/lantiq/patches-3.0/120-falcon-i2c.patch

--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
 obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_FALCON)	+= i2c-falcon.o
 
 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -282,6 +282,10 @@ config I2C_POWERMAC
 
 comment "I2C system bus drivers (mostly embedded / system-on-chip)"
 
+config I2C_FALCON
+	tristate "Falcon I2C interface"
+#	depends on SOC_FALCON
+
 config I2C_AT91
 	tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
 	depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
--- /dev/null
+++ b/drivers/i2c/busses/i2c-falcon.c
@@ -0,0 +1,803 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* #define DEBUG */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+/* CURRENT ISSUES:
+ * - no high speed support
+ * - rx issue with "address mode" & "tx end" interrupts
+ * - ten bit mode is not tested
+ */
+
+/* mapping for access macros */
+#define reg_r32(reg)		__raw_readl(reg)
+#define reg_w32(val, reg)	__raw_writel(val, reg)
+#define reg_w32_mask(clear, set, reg)	\
+				reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
+#define i2c	(priv->membase)
+#include <falcon/i2c_reg.h>
+
+/* enable hacks to overcome current issue */
+#define FALCON_FIX_ME
+
+#define FALCON_I2C_ADDR			0x00
+#define FALCON_I2C_READY_TIMEOUT	1000
+#define FALCON_I2C_WAIT_TIMEOUT		10
+
+#define DRV_NAME "i2c-falcon"
+
+#if defined(DEBUG)
+#define static /* no static functions for better debugging */
+#endif
+
+#define FALCON_I2C_ARB_LOST	(1 << 0)
+#define FALCON_I2C_NACK		(1 << 1)
+#define FALCON_I2C_RX_UFL	(1 << 2)
+#define FALCON_I2C_RX_OFL	(1 << 3)
+#define FALCON_I2C_TX_UFL	(1 << 4)
+#define FALCON_I2C_TX_OFL	(1 << 5)
+#define FALCON_I2C_BURST_REQ	(1 << 6)
+#define FALCON_I2C_RX		(1 << 7)
+#define FALCON_I2C_TX_END	(1 << 8)
+#define FALCON_I2C_ADDR_MATCH	(1 << 9) /* doesn't trigger */
+
+struct falcon_i2c {
+	spinlock_t lock;
+
+	enum {
+		FALCON_I2C_MODE_100	= 1,
+		FALCON_I2C_MODE_400	= 2,
+		FALCON_I2C_MODE_3400	= 3
+	} mode;				/* current speed mode */
+
+	int ten_bit;			/* current address mode */
+	unsigned long status;		/* bus events holder */
+	struct clk *clk;		/* clock input for i2c hardware block */
+	struct gpon_reg_i2c __iomem *membase;	/* base of mapped registers */
+	int irq_lb, irq_b, irq_err, irq_p;	/* last burst, burst, error,
+						   protocol IRQs */
+	struct completion done;
+	struct i2c_adapter adap;
+	struct device *dev;
+};
+
+#define FALCON_I2C_ERROR_MASK		(FALCON_I2C_NACK \
+					| FALCON_I2C_ARB_LOST \
+					| FALCON_I2C_RX_OFL \
+					| FALCON_I2C_RX_UFL \
+					| FALCON_I2C_TX_OFL \
+					| FALCON_I2C_TX_UFL)
+
+#define FALCON_I2C_ERROR(priv)		(priv->status & FALCON_I2C_ERROR_MASK)
+#define FALCON_I2C_ERROR_CLEAR(priv)	do { \
+						priv->status &= \
+						~FALCON_I2C_ERROR_MASK; \
+					} while (0)
+
+static void falcon_addr_configure(struct falcon_i2c *priv, int ten_bit)
+{
+	u32 ten_bit_mask = ten_bit ? I2C_ADDR_CFG_TBAM_10bit : 0;
+
+	/* configure address */
+	i2c_w32(I2C_ADDR_CFG_SOPE_EN /* generate stop when no more data in the
+					fifo */
+		| I2C_ADDR_CFG_SONA_EN /* generate stop when NA received */
+		| I2C_ADDR_CFG_MnS_EN /* we are master device */
+		| ten_bit_mask
+		| FALCON_I2C_ADDR, /* our address */
+		addr_cfg);
+}
+
+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
+{
+	u32 i_raw, i_pro, i_err;
+	struct falcon_i2c *priv = dev_id;
+	unsigned long flags;
+	unsigned int old_status;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	old_status = (unsigned int)priv->status;
+
+	i_raw = i2c_r32(mis);
+
+	/* protocol interrupt */
+	if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) {
+		i_pro = i2c_r32(p_irqss);
+
+		/* tx -> rx switch */
+		if (i_pro & I2C_P_IRQSS_RX)
+			priv->status |= FALCON_I2C_RX;
+
+		/* tx end */
+		if (i_pro & I2C_P_IRQSS_TX_END)
+			priv->status |= FALCON_I2C_TX_END;
+
+		/* not acknowledge */
+		if (i_pro & I2C_P_IRQSS_NACK)
+			priv->status |= FALCON_I2C_NACK;
+
+		/* arbitration lost */
+		if (i_pro & I2C_P_IRQSS_AL)
+			priv->status |= FALCON_I2C_ARB_LOST;
+
+		/* address match */
+		if (i_pro & I2C_P_IRQSS_AM)
+			priv->status |= FALCON_I2C_ADDR_MATCH;
+
+		i2c_w32(i_pro, p_irqsc);
+	}
+
+	/* error interrupt */
+	if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
+		i_err = i2c_r32(err_irqss);
+
+		/* tx fifo overflow */
+		if (i_err & I2C_ERR_IRQSS_TXF_OFL)
+			priv->status |= FALCON_I2C_TX_OFL;
+
+		/* tx fifo underflow */
+		if (i_err & I2C_ERR_IRQSS_TXF_UFL)
+			priv->status |= FALCON_I2C_TX_UFL;
+
+		/* rx fifo overflow */
+		if (i_err & I2C_ERR_IRQSS_RXF_OFL)
+			priv->status |= FALCON_I2C_RX_OFL;
+
+		/* rx fifo underflow */
+		if (i_err & I2C_ERR_IRQSS_RXF_UFL)
+			priv->status |= FALCON_I2C_RX_UFL;
+
+		i2c_w32(i_err, err_irqsc);
+	}
+
+	/* burst request */
+	if (i_raw & I2C_RIS_BREQ_INT_INTOCC) {
+		i2c_w32_mask(I2C_IMSC_BREQ_INT_EN, 0, imsc);
+		i2c_w32_mask(0, I2C_ICR_BREQ_INT_CLR, icr);
+
+		priv->status |= FALCON_I2C_BURST_REQ;
+	}
+
+	/* last burst request */
+	if (i_raw & I2C_RIS_LBREQ_INT_INTOCC) {
+		i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN, 0, imsc);
+		i2c_w32_mask(0, I2C_ICR_LBREQ_INT_CLR, icr);
+
+		priv->status |= FALCON_I2C_BURST_REQ;
+	}
+
+	if (old_status != (unsigned int)priv->status)
+		complete(&priv->done);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int falcon_i2c_ready(struct falcon_i2c *priv)
+{
+	int timeout;
+	u32 bus_stat;
+	unsigned long flags;
+	int ret;
+
+	for (timeout = 0; timeout < FALCON_I2C_READY_TIMEOUT; timeout++) {
+		bus_stat = i2c_r32(bus_stat);
+
+		if (bus_stat & I2C_BUS_STAT_BS_SC) {
+			cpu_relax();
+		} else {
+			spin_lock_irqsave(&priv->lock, flags);
+
+			if (FALCON_I2C_ERROR(priv)) {
+				ret = priv->status;
+
+				dev_dbg(priv->dev, "bus ready wait error 0x%08lx\n", priv->status);
+
+				FALCON_I2C_ERROR_CLEAR(priv);
+			} else {
+				ret = 0;
+			}
+
+			spin_unlock_irqrestore(&priv->lock, flags);
+
+			return ret;
+		}
+	}
+
+	dev_dbg(priv->dev, "bus ready wait timeout\n");
+
+	return -ETIME;
+}
+
+static int falcon_i2c_wait(struct falcon_i2c *priv, unsigned long status)
+{
+	int ret = 0;
+	unsigned long flags;
+	unsigned int timeout;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	priv->status &= FALCON_I2C_BURST_REQ;
+
+	/* check if the event already occurred */
+	if ((priv->status & status) == status) {
+		priv->status &= ~status;
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		return 0;
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	/* unmask burst interrupts */
+	i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
+
+	for (timeout = 0; timeout < FALCON_I2C_WAIT_TIMEOUT; timeout++) {
+		/* wait for the data request */
+		wait_for_completion_timeout(&priv->done, HZ / 10);
+
+		/* handle errors */
+		spin_lock_irqsave(&priv->lock, flags);
+
+		if (FALCON_I2C_ERROR(priv)) {
+			dev_dbg(priv->dev, "wait error 0x%08lx (waiting for 0x%08lx)\n",
+			    priv->status,
+			    status);
+
+			if (priv->status & FALCON_I2C_NACK)
+				ret = -ENXIO;
+			else
+				ret = -EREMOTEIO;
+
+			FALCON_I2C_ERROR_CLEAR(priv);
+		} else {
+			if ((priv->status & status) == status) {
+				priv->status &= ~status;
+				spin_unlock_irqrestore(&priv->lock, flags);
+
+				return 0;
+			}
+		}
+
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		if (ret)
+			return ret;
+	}
+
+	dev_dbg(priv->dev, "wait timeout error 0x%08lx (waiting for 0x%08lx)\n",
+	    priv->status,
+	    status);
+
+	return -ETIME;
+}
+
+static int falcon_i2c_tx(struct falcon_i2c *priv, int ten_bit, u16 addr,
+			 u8 *buf, int len)
+{
+	int i;
+	int ret;
+
+	dev_dbg(priv->dev, "%s\n", __func__);
+
+	/* tell fifo the number of bytes we are going to send */
+	i2c_w32(len + (ten_bit ? 2 : 1), tps_ctrl);
+
+	/* wait for the data request */
+	ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
+	if (ret)
+		return ret;
+
+	/* send slave address */
+	if (ten_bit) {
+		i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
+		i2c_w32(0x78 | ((addr & 0x7f) << 1) | 0, txd);
+	} else {
+		i2c_w32((addr << 1) | 0, txd);
+	}
+
+	/* fill fifo */
+	for (i = 0; i < len; i++) {
+		ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
+		if (ret)
+			return ret;
+
+		i2c_w32(buf[i], txd);
+	}
+
+	return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
+}
+
+static int falcon_i2c_rx(struct falcon_i2c *priv, int ten_bit, u16 addr,
+			 u8 *buf, int len)
+{
+	int i;
+	int ret;
+
+	dev_dbg(priv->dev, "%s\n", __func__);
+
+	/* we need to transmit address only */
+	i2c_w32(ten_bit ? 2 : 1, tps_ctrl);
+
+	/* set maximum received packet size */
+	i2c_w32(len, mrps_ctrl);
+
+	/* wait for the data request */
+	ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
+	if (ret)
+		return ret;
+
+	/* write down the address */
+	if (ten_bit) {
+		i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
+		i2c_w32(0x78 | ((addr & 0x7f) << 1) | 1, txd);
+	} else {
+		i2c_w32((addr << 1) | 1, txd);
+	}
+
+	/* wait for the read request */
+	ret = falcon_i2c_wait(priv, FALCON_I2C_TX_END
+#ifndef FALCON_FIX_ME
+			      | FALCON_I2C_ADDR_MATCH
+#endif
+			      | FALCON_I2C_RX);
+
+	if (ret)
+		return ret;
+
+	/* read bytes */
+	for (i = 0; i < len; i++) {
+#ifdef FALCON_FIX_ME
+		while (i2c_r32(rps_stat) == 0)
+			cpu_relax();
+#else
+		ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
+
+		if (ret)
+			return ret;
+#endif
+
+		buf[i] = i2c_r32(rxd);
+	}
+
+#ifndef FALCON_FIX_ME
+	/* wait for transmission end */
+	return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
+#else
+	return 0;
+#endif
+}
+
+static int falcon_i2c_xfer_msg(struct falcon_i2c *priv, struct i2c_msg *msg)
+{
+	int ret;
+	int ten_bit;
+	unsigned long flags;
+
+	dev_dbg(priv->dev, "%s %u byte(s) %s 0x%02x\n",
+		(msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
+		(msg->flags & I2C_M_RD) ? "from" : "to", msg->addr);
+
+	if (msg->flags & I2C_M_TEN)
+		ten_bit = 1;
+	else
+		ten_bit = 0;
+
+	/* reconfigure bus if need to send message in different address mode */
+	spin_lock_irqsave(&priv->lock, flags);
+	if (ten_bit != priv->ten_bit) {
+
+		/* disable bus */
+		i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
+
+		/* reconfigure address */
+		falcon_addr_configure(priv, ten_bit);
+
+		/* enable bus */
+		i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
+
+		priv->ten_bit = ten_bit;
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	/* read/write actual message */
+	if (msg->flags & I2C_M_RD)
+		ret = falcon_i2c_rx(priv, ten_bit, msg->addr, msg->buf,
+				    msg->len);
+	else
+		ret = falcon_i2c_tx(priv, ten_bit, msg->addr, msg->buf,
+				    msg->len);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
+			   int num)
+{
+	int i;
+	int ret;
+	unsigned long flags;
+	struct falcon_i2c *priv = i2c_get_adapdata(adap);
+
+	dev_dbg(priv->dev, "xfer %u messages\n", num);
+
+	/* transfer each message */
+	for (i = 0; i < num; i++) {
+#ifdef FALCON_FIX_ME
+		/* disable bus */
+		i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
+		/* enable bus */
+		i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
+#endif
+
+		/* clear bus status */
+		spin_lock_irqsave(&priv->lock, flags);
+		priv->status = 0;
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		/* wait for the bus to become ready */
+		ret = falcon_i2c_ready(priv);
+		if (ret)
+			return ret;
+
+		/* transfer message */
+		ret = falcon_i2c_xfer_msg(priv, &msg[i]);
+
+		if (ret)
+			return ret;
+
+		/* check for unhandled errors */
+		spin_lock_irqsave(&priv->lock, flags);
+		if (FALCON_I2C_ERROR(priv))
+			ret = priv->status;
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		if (ret) {
+			dev_warn(priv->dev, "message %u unhandled error 0x%x\n",
+				i, ret);
+
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static u32 falcon_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm falcon_i2c_algorithm = {
+	.master_xfer	= falcon_i2c_xfer,
+	.functionality	= falcon_i2c_func,
+};
+
+static int falcon_i2c_hw_init(struct i2c_adapter *adap)
+{
+	struct falcon_i2c *priv = i2c_get_adapdata(adap);
+
+	/* disable bus */
+	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
+
+	/* set normal operation clock divider */
+	i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
+
+	/* set frequency */
+	if (priv->mode == FALCON_I2C_MODE_100) {
+		dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
+
+		i2c_w32(0, fdiv_high_cfg);
+
+		i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
+			| (499 << I2C_FDIV_CFG_DEC_OFFSET),
+			fdiv_cfg);
+	} else if (priv->mode == FALCON_I2C_MODE_400) {
+		dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
+
+		i2c_w32(0, fdiv_high_cfg);
+
+		i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
+			| (124 << I2C_FDIV_CFG_DEC_OFFSET),
+			fdiv_cfg);
+	} else if (priv->mode == FALCON_I2C_MODE_3400) {
+		dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
+
+		i2c_w32(0, fdiv_cfg);
+
+		/* TODO recalculate value for 100MHz input */
+		i2c_w32((41 << I2C_FDIV_CFG_INC_OFFSET)
+			| (152 << I2C_FDIV_CFG_DEC_OFFSET),
+			fdiv_high_cfg);
+	} else {
+		dev_warn(priv->dev, "unknown mode\n");
+
+		return -ENODEV;
+	}
+
+	/* configure fifo */
+	i2c_w32(I2C_FIFO_CFG_TXFC /* tx fifo as flow controller */
+		| I2C_FIFO_CFG_RXFC /* rx fifo as flow controller */
+		| I2C_FIFO_CFG_TXFA_TXFA2 /* tx fifo 4-byte aligned */
+		| I2C_FIFO_CFG_RXFA_RXFA2 /* rx fifo 4-byte aligned */
+		| I2C_FIFO_CFG_TXBS_TXBS0 /* tx fifo burst size is 1 word */
+		| I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
+		fifo_cfg);
+
+	/* configure address */
+	falcon_addr_configure(priv, priv->ten_bit);
+
+	/* enable bus */
+	i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
+
+	/* mask burst interrupts */
+	i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
+
+	/* enable interrupts */
+	i2c_w32(I2C_IMSC_LBREQ_INT_EN
+		| I2C_IMSC_BREQ_INT_EN
+		| I2C_IMSC_I2C_P_INT_EN
+		| I2C_IMSC_I2C_ERR_INT_EN,
+		imsc);
+
+	return 0;
+}
+
+static int __devinit falcon_i2c_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct falcon_i2c *priv;
+	struct i2c_adapter *adap;
+	struct resource *mmres, *ioarea,
+			*irqres_lb, *irqres_b, *irqres_err, *irqres_p;
+	struct clk *clk;
+
+	dev_dbg(&pdev->dev, "probing\n");
+
+	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+						 "i2c_lb");
+	irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
+	irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+						  "i2c_err");
+	irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
+
+	if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
+		dev_err(&pdev->dev, "no resources\n");
+		return -ENODEV;
+	}
+
+	clk = clk_get(&pdev->dev, "fpi");
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "failed to get fpi clk\n");
+		return -ENOENT;
+	}
+
+	if (clk_get_rate(clk) != 100000000) {
+		dev_err(&pdev->dev, "input clock is not 100MHz\n");
+		return -ENOENT;
+	}
+
+	/* allocate private data */
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(&pdev->dev, "can't allocate private data\n");
+		return -ENOMEM;
+	}
+
+	adap = &priv->adap;
+	i2c_set_adapdata(adap, priv);
+	adap->owner = THIS_MODULE;
+	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+	strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
+	adap->algo = &falcon_i2c_algorithm;
+
+	priv->ten_bit = 0;
+	priv->mode = FALCON_I2C_MODE_100;
+	priv->clk = clk;
+	priv->dev = &pdev->dev;
+
+	spin_lock_init(&priv->lock);
+
+	ioarea = request_mem_region(mmres->start, resource_size(mmres),
+					 pdev->name);
+
+	if (ioarea == NULL) {
+		dev_err(&pdev->dev, "I2C region already claimed\n");
+		ret = -ENXIO;
+		goto err_free_priv;
+	}
+
+	/* map memory */
+	priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
+		resource_size(mmres));
+	if (priv->membase == NULL) {
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
+	priv->irq_lb = irqres_lb->start;
+	ret = request_irq(priv->irq_lb, falcon_i2c_isr, IRQF_DISABLED,
+			  irqres_lb->name, priv);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
+		ret = -ENODEV;
+		goto err_unmap_mem;
+	}
+
+	priv->irq_b = irqres_b->start;
+	ret = request_irq(priv->irq_b, falcon_i2c_isr, IRQF_DISABLED,
+			  irqres_b->name, priv);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
+		ret = -ENODEV;
+		goto err_free_lb_irq;
+	}
+
+	priv->irq_err = irqres_err->start;
+	ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
+			  irqres_err->name, priv);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
+		ret = -ENODEV;
+		goto err_free_b_irq;
+	}
+
+	priv->irq_p = irqres_p->start;
+	ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
+			  irqres_p->name, priv);
+	if (ret) {
+		dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
+		ret = -ENODEV;
+		goto err_free_err_irq;
+	}
+
+	dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
+	dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
+	    irqres_b->start, irqres_err->start, irqres_p->start);
+
+	/* add our adapter to the i2c stack */
+	ret = i2c_add_numbered_adapter(adap);
+	if (ret) {
+		dev_err(&pdev->dev, "can't register I2C adapter\n");
+		goto err_free_p_irq;
+	}
+
+	platform_set_drvdata(pdev, priv);
+	i2c_set_adapdata(adap, priv);
+
+	/* print module version information */
+	dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
+		(i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
+		(i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
+
+	init_completion(&priv->done);
+
+	/* initialize HW */
+	ret = falcon_i2c_hw_init(adap);
+	if (ret) {
+		dev_err(&pdev->dev, "can't configure adapter\n");
+		goto err_remove_adapter;
+	}
+
+	return 0;
+
+err_remove_adapter:
+	i2c_del_adapter(adap);
+	platform_set_drvdata(pdev, NULL);
+
+err_free_p_irq:
+	free_irq(priv->irq_p, priv);
+
+err_free_err_irq:
+	free_irq(priv->irq_err, priv);
+
+err_free_b_irq:
+	free_irq(priv->irq_b, priv);
+
+err_free_lb_irq:
+	free_irq(priv->irq_lb, priv);
+
+err_unmap_mem:
+	iounmap(priv->membase);
+
+err_release_region:
+	release_mem_region(mmres->start, resource_size(mmres));
+
+err_free_priv:
+	kfree(priv);
+
+	return ret;
+}
+
+static int __devexit falcon_i2c_remove(struct platform_device *pdev)
+{
+	struct falcon_i2c *priv = platform_get_drvdata(pdev);
+	struct resource *mmres;
+
+	/* disable bus */
+	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
+
+	/* remove driver */
+	platform_set_drvdata(pdev, NULL);
+	i2c_del_adapter(&priv->adap);
+
+	free_irq(priv->irq_lb, priv);
+	free_irq(priv->irq_b, priv);
+	free_irq(priv->irq_err, priv);
+	free_irq(priv->irq_p, priv);
+
+	kfree(priv);
+
+	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(mmres->start, resource_size(mmres));
+
+	dev_dbg(&pdev->dev, "removed\n");
+
+	return 0;
+}
+
+static struct platform_driver falcon_i2c_driver = {
+	.probe	= falcon_i2c_probe,
+	.remove	= __devexit_p(falcon_i2c_remove),
+	.driver	= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init falcon_i2c_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&falcon_i2c_driver);
+
+	if (ret)
+		printk(KERN_DEBUG DRV_NAME ": can't register platform driver");
+
+	return ret;
+}
+
+static void __exit falcon_i2c_exit(void)
+{
+	platform_driver_unregister(&falcon_i2c_driver);
+}
+
+module_init(falcon_i2c_init);
+module_exit(falcon_i2c_exit);
+
+MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
+MODULE_ALIAS("platform:i2c_falcon");
+MODULE_LICENSE("GPL");