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1a29ef8e97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19815 3c298f89-4303-0410-b956-a3cf2f4a3e73
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* arch/ubicom32/include/asm/cacheflush.h
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* Cache flushing definitions for Ubicom32 architecture.
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*
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* (C) Copyright 2009, Ubicom, Inc.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can redistribute
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* it and/or modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, either version 2 of the
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* License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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*
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* Ubicom32 implementation derived from (with many thanks):
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* arch/m68knommu
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* arch/blackfin
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* arch/parisc
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*/
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#ifndef _ASM_UBICOM32_CACHEFLUSH_H
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#define _ASM_UBICOM32_CACHEFLUSH_H
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/*
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* (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
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*/
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#include <linux/mm.h>
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#include <asm/cachectl.h>
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#include <asm/ip5000.h>
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#define flush_cache_all() __flush_cache_all()
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) __flush_cache_all()
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#define flush_cache_page(vma, vmaddr) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_dcache_range(start, end) \
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do { \
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/* Flush the data cache and invalidate the I cache. */ \
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mem_cache_control(DCCR_BASE, start, end, CCR_CTRL_FLUSH_ADDR); \
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mem_cache_control(ICCR_BASE, start, end, CCR_CTRL_INV_ADDR); \
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} while (0)
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#define flush_icache_range(start, end) \
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do { \
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/* Flush the data cache and invalidate the I cache. */ \
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mem_cache_control(DCCR_BASE, start, end, CCR_CTRL_FLUSH_ADDR); \
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mem_cache_control(ICCR_BASE, start, end, CCR_CTRL_INV_ADDR); \
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} while (0)
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#define flush_icache_page(vma,pg) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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/*
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* Cache handling for IP5000
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*/
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extern inline void mem_cache_invalidate_all(unsigned long cc)
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{
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if (cc == DCCR_BASE)
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UBICOM32_LOCK(DCCR_LOCK_BIT);
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else
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UBICOM32_LOCK(ICCR_LOCK_BIT);
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asm volatile (
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" bset "D(CCR_CTRL)"(%0), "D(CCR_CTRL)"(%0), #"D(CCR_CTRL_RESET)" \n\t"
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" nop \n\t"
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" bclr "D(CCR_CTRL)"(%0), "D(CCR_CTRL)"(%0), #"D(CCR_CTRL_RESET)" \n\t"
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" pipe_flush 0 \n\t"
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:
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: "a"(cc)
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: "cc"
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);
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if (cc == DCCR_BASE)
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UBICOM32_UNLOCK(DCCR_LOCK_BIT);
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else
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UBICOM32_UNLOCK(ICCR_LOCK_BIT);
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}
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static inline void __flush_cache_all(void)
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{
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/*
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* Flush Icache
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*/
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mem_cache_invalidate_all(ICCR_BASE);
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/*
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* Flush Dcache
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*/
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mem_cache_invalidate_all(DCCR_BASE);
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}
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#endif /* _ASM_UBICOM32_CACHEFLUSH_H */
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