mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-21 17:06:46 +02:00
8e13cb8141
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14215 3c298f89-4303-0410-b956-a3cf2f4a3e73
136 lines
4.7 KiB
Diff
136 lines
4.7 KiB
Diff
--- a/ath_hal/ah_os.h
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+++ b/ath_hal/ah_os.h
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@@ -156,80 +156,23 @@ extern u_int32_t __ahdecl ath_hal_getupt
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#endif
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#endif /* AH_BYTE_ORDER */
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-/*
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- * Some big-endian architectures don't set CONFIG_GENERIC_IOMAP, but fail to
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- * implement iowrite32be and ioread32be. Provide compatibility macros when
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- * it's needed.
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- *
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- * As of Linux 2.6.24, only MIPS, PARISC and PowerPC implement iowrite32be and
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- * ioread32be as functions.
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- *
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- * The downside or the replacement macros it that we may be byte-swapping data
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- * for the second time, so the native implementations should be preferred.
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- */
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-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) && \
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- !defined(CONFIG_GENERIC_IOMAP) && (AH_BYTE_ORDER == AH_BIG_ENDIAN) && \
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- !defined(__mips__) && !defined(__hppa__) && !defined(__powerpc__)
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-# ifndef iowrite32be
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-# define iowrite32be(_val, _addr) iowrite32(swab32((_val)), (_addr))
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-# endif
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-# ifndef ioread32be
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-# define ioread32be(_addr) swab32(ioread32((_addr)))
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-# endif
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-#endif
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+#define IS_SWAPPED(_ah, _reg) \
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+ ((_ah)->ah_swapped && \
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+ (((0x4000 <= (_reg)) && ((_reg) < 0x5000)) || \
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+ ((0x7000 <= (_reg)) && ((_reg) < 0x8000))))
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+
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+#define SWAPREG(_ah, _reg, _val) \
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+ (IS_SWAPPED(_ah, _reg) ? cpu_to_le32(_val) : (_val))
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/*
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* The register accesses are done using target-specific functions when
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* debugging is enabled (AH_DEBUG) or it's explicitly requested for the target.
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- *
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- * The hardware registers use little-endian byte order natively. Big-endian
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- * systems are configured by HAL to enable hardware byte-swap of register reads
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- * and writes at reset. This avoid the need to byte-swap the data in software.
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- * However, the registers in a certain area from 0x4000 to 0x4fff (PCI clock
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- * domain registers) are not byte swapped!
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- *
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- * Since Linux I/O primitives default to little-endian operations, we only
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- * need to suppress byte-swapping on big-endian systems outside the area used
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- * by the PCI clock domain registers.
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*/
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-#if (AH_BYTE_ORDER == AH_BIG_ENDIAN)
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-#define is_reg_le(__reg) ((0x4000 <= (__reg) && (__reg) < 0x5000))
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-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)
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-#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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- is_reg_le(_reg) ? \
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- iowrite32((_val), (_ah)->ah_sh + (_reg)) : \
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- iowrite32be((_val), (_ah)->ah_sh + (_reg)); \
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- } while (0)
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-#define _OS_REG_READ(_ah, _reg) \
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- (is_reg_le(_reg) ? \
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- ioread32((_ah)->ah_sh + (_reg)) : \
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- ioread32be((_ah)->ah_sh + (_reg)))
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-#else
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-#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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- writel(is_reg_le(_reg) ? \
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- (_val) : cpu_to_le32(_val), \
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- (_ah)->ah_sh + (_reg)); \
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- } while (0)
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-#define _OS_REG_READ(_ah, _reg) \
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- (is_reg_le(_reg) ? \
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- readl((_ah)->ah_sh + (_reg)) : \
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- cpu_to_le32(readl((_ah)->ah_sh + (_reg))))
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-#endif /* KERNEL_VERSION(2,6,12) */
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-#else /* AH_BYTE_ORDER != AH_BIG_ENDIAN */
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-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)
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-#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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- iowrite32((_val), (_ah)->ah_sh + (_reg)); \
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- } while (0)
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-#define _OS_REG_READ(_ah, _reg) \
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- ioread32((_ah)->ah_sh + (_reg))
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-#else
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#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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- writel((_val), (_ah)->ah_sh + (_reg)); \
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- } while (0)
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+ __raw_writel(SWAPREG(_ah, _reg, _val), (_ah)->ah_sh + (_reg)); \
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+} while (0)
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#define _OS_REG_READ(_ah, _reg) \
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- readl((_ah)->ah_sh + (_reg))
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-#endif /* KERNEL_VERSION(2,6,12) */
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-#endif /* AH_BYTE_ORDER != AH_BIG_ENDIAN */
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+ SWAPREG(_ah, _reg, __raw_readl((_ah)->ah_sh + (_reg)))
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/*
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* The functions in this section are not intended to be invoked by MadWifi
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--- a/ath/if_ath.c
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+++ b/ath/if_ath.c
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@@ -606,6 +606,14 @@ ath_attach(u_int16_t devid, struct net_d
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}
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sc->sc_ah = ah;
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+ /* WAR for AR7100 PCI bug */
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+#ifdef CONFIG_ATHEROS_AR71XX
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+ if ((ar_device(sc->devid) >= 5210) && (ar_device(sc->devid) < 5416)) {
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+ ath_hal_setcapability(ah, HAL_CAP_DMABURST_RX, 0, HAL_DMABURST_4B, NULL);
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+ ath_hal_setcapability(ah, HAL_CAP_DMABURST_TX, 0, HAL_DMABURST_4B, NULL);
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+ }
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+#endif
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+
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/*
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* Check if the MAC has multi-rate retry support.
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* We do this by trying to setup a fake extended
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@@ -7555,7 +7563,7 @@ ath_txq_setup(struct ath_softc *sc, int
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if (qtype == HAL_TX_QUEUE_UAPSD)
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qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
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else
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- qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
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+ qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXOKINT_ENABLE |
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HAL_TXQ_TXDESCINT_ENABLE;
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qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
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if (qnum == -1) {
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--- a/ath_hal/ah_os.c
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+++ b/ath_hal/ah_os.c
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@@ -126,6 +126,13 @@ ath_hal_printf(struct ath_hal *ah, const
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}
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EXPORT_SYMBOL(ath_hal_printf);
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+void __ahdecl
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+ath_hal_printstr(struct ath_hal *ah, const char *str)
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+{
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+ printk("%s", str);
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+}
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+EXPORT_SYMBOL(ath_hal_printstr);
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+
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/*
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* Format an Ethernet MAC for printing.
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*/
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