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git://projects.qi-hardware.com/openwrt-xburst.git
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b06573b702
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12863 3c298f89-4303-0410-b956-a3cf2f4a3e73
278 lines
6.4 KiB
C
278 lines
6.4 KiB
C
/*
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* ADM5120 PCI Host Controller driver
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*
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* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
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*
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* This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
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* done by Jeroen Vreeken
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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*
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* Jeroen's code was based on the Linux 2.4.xx source codes found in various
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* tarballs released by Edimax for it's ADM5120 based devices
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* Copyright (C) ADMtek Incorporated
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <asm/delay.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_platform.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(f, a...) printk(KERN_DEBUG f, ## a)
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#else
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#define DBG(f, a...) do {} while (0)
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#endif
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#define PCI_ENABLE 0x80000000
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/* -------------------------------------------------------------------------*/
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static unsigned int adm5120_pci_nr_irqs __initdata;
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static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
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static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
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/* -------------------------------------------------------------------------*/
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static inline void write_cfgaddr(u32 addr)
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{
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__raw_writel((addr | PCI_ENABLE),
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(void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
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}
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static inline void write_cfgdata(u32 data)
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{
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__raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 read_cfgdata(void)
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{
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return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
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(where & 0xFC));
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}
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/* -------------------------------------------------------------------------*/
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus, devfn, where));
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data = read_cfgdata();
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DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, data);
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*val = data;
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DBG(", 0x%08X returned\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus, devfn, where));
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data = read_cfgdata();
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DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, data);
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((val & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((val & 0xFFFF) << s);
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break;
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case 4:
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data = val;
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break;
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}
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write_cfgdata(data);
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DBG(", 0x%08X written\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm5120_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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/* -------------------------------------------------------------------------*/
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static void adm5120_pci_fixup(struct pci_dev *dev)
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{
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if (dev->devfn != 0)
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return;
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/* setup COMMAND register */
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pci_write_config_word(dev, PCI_COMMAND,
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(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* setup CACHE_LINE_SIZE register */
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
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/* setup BARS */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
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adm5120_pci_fixup);
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/* -------------------------------------------------------------------------*/
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void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
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struct adm5120_pci_irq *map)
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{
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adm5120_pci_nr_irqs = nr_irqs;
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adm5120_pci_irq_map = map;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = -1;
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int i;
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if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
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printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
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goto out;
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}
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if (slot < 1 || slot > 3) {
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printk(KERN_ALERT "PCI: slot number %u is not supported\n",
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slot);
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goto out;
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}
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for (i = 0; i < adm5120_pci_nr_irqs; i++) {
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if ((adm5120_pci_irq_map[i].slot == slot)
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&& (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
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&& (adm5120_pci_irq_map[i].pin == pin)) {
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irq = adm5120_pci_irq_map[i].irq;
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break;
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}
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}
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if (irq < 0) {
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printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
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pci_name((struct pci_dev *)dev), pin);
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} else {
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printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
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pci_name((struct pci_dev *)dev), pin, irq);
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}
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out:
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return irq;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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/* -------------------------------------------------------------------------*/
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static struct resource pci_io_resource = {
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.name = "ADM5120 PCI I/O",
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.start = ADM5120_PCIIO_BASE,
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.end = ADM5120_PCICFG_ADDR-1,
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.name = "ADM5120 PCI MEM",
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.start = ADM5120_PCIMEM_BASE,
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.end = ADM5120_PCIIO_BASE-1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller adm5120_controller = {
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.pci_ops = &adm5120_pci_ops,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource,
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};
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static int __init adm5120_pci_setup(void)
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{
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if (adm5120_package_pqfp()) {
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printk(KERN_INFO "PCI: not available on ADM5120P\n");
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return -1;
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}
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/* Avoid ISA compat ranges. */
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PCIBIOS_MIN_IO = 0x00000000;
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PCIBIOS_MIN_MEM = 0x00000000;
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/* Set I/O resource limits. */
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ioport_resource.end = 0x1fffffff;
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iomem_resource.end = 0xffffffff;
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register_pci_controller(&adm5120_controller);
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return 0;
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}
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arch_initcall(adm5120_pci_setup);
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