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d68bc110c8
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13860 3c298f89-4303-0410-b956-a3cf2f4a3e73
69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
/*
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* Atheros PB42 board support
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <asm/mips_machine.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#include <asm/mach-ar71xx/platform.h>
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static struct spi_board_info pb42_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p80",
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}
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};
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static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
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{
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.slot = 0,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV0,
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}, {
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.slot = 1,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV1,
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}, {
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.slot = 2,
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.pin = 1,
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.irq = AR71XX_PCI_IRQ_DEV2,
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}
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};
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static void __init pb42_init(void)
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{
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ar71xx_add_device_spi(NULL, pb42_spi_info,
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ARRAY_SIZE(pb42_spi_info));
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ar71xx_add_device_mdio(0xffe0ffff);
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ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ar71xx_eth0_data.phy_mask = 0x000f0000;
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ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
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ar71xx_eth1_data.phy_mask = 0x00100000;
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ar71xx_add_device_eth(0);
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ar71xx_add_device_eth(1);
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ar71xx_add_device_usb();
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ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
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}
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MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);
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