mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-10-30 09:29:41 +02:00
284a2e1864
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12311 3c298f89-4303-0410-b956-a3cf2f4a3e73
160 lines
3.9 KiB
Diff
160 lines
3.9 KiB
Diff
Allow registering PCI devices after early boot.
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This is an ugly hack and needs to be rewritten before going upstream.
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--- a/arch/mips/pci/pci.c
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+++ b/arch/mips/pci/pci.c
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@@ -21,6 +21,17 @@
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*/
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int pci_probe_only;
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+/*
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+ * Indicate whether PCI-bios init was already done.
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+ */
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+static int pcibios_init_done;
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+
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+/*
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+ * The currently used busnumber.
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+ */
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+static int next_busno;
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+static int need_domain_info;
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+
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#define PCI_ASSIGN_ALL_BUSSES 1
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unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
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@@ -75,8 +86,32 @@
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res->start = start;
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}
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-void __devinit register_pci_controller(struct pci_controller *hose)
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+/* Most MIPS systems have straight-forward swizzling needs. */
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+
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+static inline u8 bridge_swizzle(u8 pin, u8 slot)
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+{
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+ return (((pin - 1) + slot) % 4) + 1;
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+}
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+
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+static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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+ u8 pin = *pinp;
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+
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+ while (dev->bus->parent) {
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+ pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
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+ /* Move up the chain of bridges. */
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+ dev = dev->bus->self;
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+ }
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+ *pinp = pin;
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+
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+ /* The slot is the slot of the last bridge. */
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+ return PCI_SLOT(dev->devfn);
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+}
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+
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+void register_pci_controller(struct pci_controller *hose)
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+{
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+ struct pci_bus *bus;
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+
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if (request_resource(&iomem_resource, hose->mem_resource) < 0)
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goto out;
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if (request_resource(&ioport_resource, hose->io_resource) < 0) {
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@@ -84,9 +119,6 @@
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goto out;
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}
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- *hose_tail = hose;
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- hose_tail = &hose->next;
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-
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/*
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* Do not panic here but later - this might hapen before console init.
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*/
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@@ -94,41 +126,47 @@
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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- return;
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-out:
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- printk(KERN_WARNING
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- "Skipping PCI bus scan due to resource conflict\n");
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-}
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+ if (pcibios_init_done) {
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+ //TODO
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-/* Most MIPS systems have straight-forward swizzling needs. */
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+ printk(KERN_INFO "Registering a PCI bus after boot\n");
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-static inline u8 bridge_swizzle(u8 pin, u8 slot)
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-{
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- return (((pin - 1) + slot) % 4) + 1;
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-}
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+ if (!hose->iommu)
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+ PCI_DMA_BUS_IS_PHYS = 1;
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-static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
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-{
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- u8 pin = *pinp;
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+ bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
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+ hose->bus = bus;
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+ need_domain_info = need_domain_info || hose->index;
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+ hose->need_domain_info = need_domain_info;
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+ if (bus) {
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+ next_busno = bus->subordinate + 1;
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+ /* Don't allow 8-bit bus number overflow inside the hose -
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+ reserve some space for bridges. */
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+ if (next_busno > 224) {
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+ next_busno = 0;
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+ need_domain_info = 1;
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+ }
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+ }
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+ if (!pci_probe_only)
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+ pci_assign_unassigned_resources();
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+ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
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+ } else {
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+ *hose_tail = hose;
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+ hose_tail = &hose->next;
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+ }
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- while (dev->bus->parent) {
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- pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
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- /* Move up the chain of bridges. */
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- dev = dev->bus->self;
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- }
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- *pinp = pin;
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+ return;
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- /* The slot is the slot of the last bridge. */
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- return PCI_SLOT(dev->devfn);
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+out:
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+ printk(KERN_WARNING
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+ "Skipping PCI bus scan due to resource conflict\n");
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose;
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struct pci_bus *bus;
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- int next_busno;
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- int need_domain_info = 0;
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/* Scan all of the recorded PCI controllers. */
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for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
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@@ -157,6 +195,7 @@
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if (!pci_probe_only)
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pci_assign_unassigned_resources();
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pci_fixup_irqs(common_swizzle, pcibios_map_irq);
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+ pcibios_init_done = 1;
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return 0;
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}
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1185,9 +1185,7 @@
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/* ssb must be initialized after PCI but before the ssb drivers.
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* That means we must use some initcall between subsys_initcall
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* and device_initcall. */
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-//FIXME on embedded we need to be early to make sure we can register
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-// a new PCI bus, if needed.
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-subsys_initcall(ssb_modinit);
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+fs_initcall(ssb_modinit);
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static void __exit ssb_modexit(void)
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{
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