mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 22:44:59 +02:00
22c1090f91
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11597 3c298f89-4303-0410-b956-a3cf2f4a3e73
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_irq.h>
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#include <asm/addrspace.h>
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#include <linux/vmalloc.h>
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#include <asm/ifxmips/ifxmips_ebu.h>
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#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
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#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
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#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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extern u32 ifxmips_pci_mapped_cfg;
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static int
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ifxmips_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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{
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unsigned long cfg_base;
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unsigned long flags;
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u32 temp;
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/* IFXMips support slot from 0 to 15 */
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/* dev_fn 0&0x68 (AD29) is ifxmips itself */
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if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
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|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
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return 1;
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spin_lock_irqsave(&ebu_lock, flags);
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cfg_base = ifxmips_pci_mapped_cfg;
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cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
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IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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/* Perform access */
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if (access_type == PCI_ACCESS_WRITE)
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{
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#ifdef CONFIG_SWAP_IO_SPACE
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ifxmips_w32(swab32(*data), ((u32*)cfg_base));
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#else
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ifxmips_w32(*data, ((u32*)cfg_base));
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#endif
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} else {
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*data = ifxmips_r32(((u32*)(cfg_base)));
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#ifdef CONFIG_SWAP_IO_SPACE
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*data = swab32(*data);
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#endif
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}
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wmb();
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/* clean possible Master abort */
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cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
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temp = ifxmips_r32(((u32*)(cfg_base)));
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#ifdef CONFIG_SWAP_IO_SPACE
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temp = swab32 (temp);
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#endif
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cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
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ifxmips_w32(temp, ((u32*)cfg_base));
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spin_unlock_irqrestore(&ebu_lock, flags);
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if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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return 1;
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return 0;
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}
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int
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ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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int
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ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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{
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data = val;
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} else {
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if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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